adder.tan.qmsg

本设计是用32位的并行全加器的,可以实现浮点运算!

{ "Info" "ITDB_TSU_RESULT" "Q\[31\]~reg0 D2\[19\] ENABLE 9.027 ns register " "Info: tsu for register \"Q\[31\]~reg0\" (data pin = \"D2\[19\]\", clock pin = \"ENABLE\") is 9.027 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.944 ns + Longest pin register " "Info: + Longest pin to register delay is 11.944 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns D2\[19\] 1 PIN PIN_158 3 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_158; Fanout = 3; PIN Node = 'D2\[19\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { D2[19] } "NODE_NAME" } } { "ADDER.vhd" "" { Text "F:/FPGA/ADDER/ADDER/ADDER.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(8.550 ns) + CELL(0.564 ns) 10.583 ns Q\[19\]~199 2 COMB LC_X5_Y18_N3 2 " "Info: 2: + IC(8.550 ns) + CELL(0.564 ns) = 10.583 ns; Loc. = LC_X5_Y18_N3; Fanout = 2; COMB Node = 'Q\[19\]~199'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "9.114 ns" { D2[19] Q[19]~199 } "NODE_NAME" } } { "ADDER.vhd" "" { Text "F:/FPGA/ADDER/ADDER/ADDER.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 10.761 ns Q\[20\]~201 3 COMB LC_X5_Y18_N4 6 " "Info: 3: + IC(0.000 ns) + CELL(0.178 ns) = 10.761 ns; Loc. = LC_X5_Y18_N4; Fanout = 6; COMB Node = 'Q\[20\]~201'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.178 ns" { Q[19]~199 Q[20]~201 } "NODE_NAME" } } { "ADDER.vhd" "" { Text "F:/FPGA/ADDER/ADDER/ADDER.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 10.969 ns Q\[25\]~211 4 COMB LC_X5_Y18_N9 6 " "Info: 4: + IC(0.000 ns) + CELL(0.208 ns) = 10.969 ns; Loc. = LC_X5_Y18_N9; Fanout = 6; COMB Node = 'Q\[25\]~211'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.208 ns" { Q[20]~201 Q[25]~211 } "NODE_NAME" } } { "ADDER.vhd" "" { Text "F:/FPGA/ADDER/ADDER/ADDER.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 11.105 ns Q\[30\]~221 5 COMB LC_X5_Y17_N4 1 " "Info: 5: + IC(0.000 ns) + CELL(0.136 ns) = 11.105 ns; Loc. = LC_X5_Y17_N4; Fanout = 1; COMB Node = 'Q\[30\]~221'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { Q[25]~211 Q[30]~221 } "NODE_NAME" } } { "ADDER.vhd" "" { Text "F:/FPGA/ADDER/ADDER/ADDER.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 11.944 ns Q\[31\]~reg0 6 REG LC_X5_Y17_N5 1 " "Info: 6: + IC(0.000 ns) + CELL(0.839 ns) = 11.944 ns; Loc. = LC_X5_Y17_N5; Fanout = 1; REG Node = 'Q\[31\]~reg0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.839 ns" { Q[30]~221 Q[31]~reg0 } "NODE_NAME" } } { "ADDER.vhd" "" { Text "F:/FPGA/ADDER/ADDER/ADDER.vhd" 21 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.394 ns ( 28.42 % ) " "Info: Total cell delay = 3.394 ns ( 28.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.550 ns ( 71.58 % ) " "Info: Total interconnect delay = 8.550 ns ( 71.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "11.944 ns" { D2[19] Q[19]~199 Q[20]~201 Q[25]~211 Q[30]~221 Q[31]~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "11.944 ns" { D2[19] {} D2[19]~out0 {} Q[19]~199 {} Q[20]~201 {} Q[25]~211 {} Q[30]~221 {} Q[31]~reg0 {} } { 0.000ns 0.000ns 8.550ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.469ns 0.564ns 0.178ns 0.208ns 0.136ns 0.839ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "ADDER.vhd" "" { Text "F:/FPGA/ADDER/ADDER/ADDER.vhd" 21 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ENABLE destination 2.954 ns - Shortest register " "Info: - Shortest clock path from clock \"ENABLE\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns ENABLE 1 CLK PIN_29 32 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 32; CLK Node = 'ENABLE'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { ENABLE } "NODE_NAME" } } { "ADDER.vhd" "" { Text "F:/FPGA/ADDER/ADDER/ADDER.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns Q\[31\]~reg0 2 REG LC_X5_Y17_N5 1 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X5_Y17_N5; Fanout = 1; REG Node = 'Q\[31\]~reg0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { ENABLE Q[31]~reg0 } "NODE_NAME" } } { "ADDER.vhd" "" { Text "F:/FPGA/ADDER/ADDER/ADDER.vhd" 21 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { ENABLE Q[31]~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { ENABLE {} ENABLE~out0 {} Q[31]~reg0 {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "11.944 ns" { D2[19] Q[19]~199 Q[20]~201 Q[25]~211 Q[30]~221 Q[31]~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "11.944 ns" { D2[19] {} D2[19]~out0 {} Q[19]~199 {} Q[20]~201 {} Q[25]~211 {} Q[30]~221 {} Q[31]~reg0 {} } { 0.000ns 0.000ns 8.550ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.469ns 0.564ns 0.178ns 0.208ns 0.136ns 0.839ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { ENABLE Q[31]~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { ENABLE {} ENABLE~out0 {} Q[31]~reg0 {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "ENABLE Q\[28\] Q\[28\]~reg0 9.606 ns register " "Info: tco from clock \"ENABLE\" to destination pin \"Q\[28\]\" through register \"Q\[28\]~reg0\" is 9.606 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ENABLE source 2.954 ns + Longest register " "Info: + Longest clock path from clock \"ENABLE\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns ENABLE 1 CLK PIN_29 32 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 32; CLK Node = 'ENABLE'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { ENABLE } "NODE_NAME" } } { "ADDER.vhd" "" { Text "F:/FPGA/ADDER/ADDER/ADDER.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns Q\[28\]~reg0 2 REG LC_X5_Y17_N2 1 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X5_Y17_N2; Fanout = 1; REG Node = 'Q\[28\]~reg0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { ENABLE Q[28]~reg0 } "NODE_NAME" } } { "ADDER.vhd" "" { Text "F:/FPGA/ADDER/ADDER/ADDER.vhd" 21 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { ENABLE Q[28]~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { ENABLE {} ENABLE~out0 {} Q[28]~reg0 {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "ADDER.vhd" "" { Text "F:/FPGA/ADDER/ADDER/ADDER.vhd" 21 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.428 ns + Longest register pin " "Info: + Longest register to pin delay is 6.428 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Q\[28\]~reg0 1 REG LC_X5_Y17_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y17_N2; Fanout = 1; REG Node = 'Q\[28\]~reg0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Q[28]~reg0 } "NODE_NAME" } } { "ADDER.vhd" "" { Text "F:/FPGA/ADDER/ADDER/ADDER.vhd" 21 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.320 ns) + CELL(2.108 ns) 6.428 ns Q\[28\] 2 PIN PIN_96 0 " "Info: 2: + IC(4.320 ns) + CELL(2.108 ns) = 6.428 ns; Loc. = PIN_96; Fanout = 0; PIN Node = 'Q\[28\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.428 ns" { Q[28]~reg0 Q[28] } "NODE_NAME" } } { "ADDER.vhd" "" { Text "F:/FPGA/ADDER/ADDER/ADDER.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 32.79 % ) " "Info: Total cell delay = 2.108 ns ( 32.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.320 ns ( 67.21 % ) " "Info: Total interconnect delay = 4.320 ns ( 67.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.428 ns" { Q[28]~reg0 Q[28] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.428 ns" { Q[28]~reg0 {} Q[28] {} } { 0.000ns 4.320ns } { 0.000ns 2.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { ENABLE Q[28]~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { ENABLE {} ENABLE~out0 {} Q[28]~reg0 {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.428 ns" { Q[28]~reg0 Q[28] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.428 ns" { Q[28]~reg0 {} Q[28] {} } { 0.000ns 4.320ns } { 0.000ns 2.108ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "Q\[23\]~reg0 D1\[23\] ENABLE -4.158 ns register " "Info: th for register \"Q\[23\]~reg0\" (data pin = \"D1\[23\]\", clock pin = \"ENABLE\") is -4.158 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ENABLE destination 2.954 ns + Longest register " "Info: + Longest clock path from clock \"ENABLE\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns ENABLE 1 CLK PIN_29 32 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 32; CLK Node = 'ENABLE'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { ENABLE } "NODE_NAME" } } { "ADDER.vhd" "" { Text "F:/FPGA/ADDER/ADDER/ADDER.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns Q\[23\]~reg0 2 REG LC_X5_Y18_N7 1 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X5_Y18_N7; Fanout = 1; REG Node = 'Q\[23\]~reg0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { ENABLE Q[23]~reg0 } "NODE_NAME" } } { "ADDER.vhd" "" { Text "F:/FPGA/ADDER/ADDER/ADDER.vhd" 21 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { ENABLE Q[23]~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { ENABLE {} ENABLE~out0 {} Q[23]~reg0 {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "ADDER.vhd" "" { Text "F:/FPGA/ADDER/ADDER/ADDER.vhd" 21 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.127 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.127 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns D1\[23\] 1 PIN PIN_234 3 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_234; Fanout = 3; PIN Node = 'D1\[23\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { D1[23] } "NODE_NAME" } } { "ADDER.vhd" "" { Text "F:/FPGA/ADDER/ADDER/ADDER.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.045 ns) + CELL(0.607 ns) 7.127 ns Q\[23\]~reg0 2 REG LC_X5_Y18_N7 1 " "Info: 2: + IC(5.045 ns) + CELL(0.607 ns) = 7.127 ns; Loc. = LC_X5_Y18_N7; Fanout = 1; REG Node = 'Q\[23\]~reg0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.652 ns" { D1[23] Q[23]~reg0 } "NODE_NAME" } } { "ADDER.vhd" "" { Text "F:/FPGA/ADDER/ADDER/ADDER.vhd" 21 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.082 ns ( 29.21 % ) " "Info: Total cell delay = 2.082 ns ( 29.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.045 ns ( 70.79 % ) " "Info: Total interconnect delay = 5.045 ns ( 70.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.127 ns" { D1[23] Q[23]~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.127 ns" { D1[23] {} D1[23]~out0 {} Q[23]~reg0 {} } { 0.000ns 0.000ns 5.045ns } { 0.000ns 1.475ns 0.607ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { ENABLE Q[23]~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { ENABLE {} ENABLE~out0 {} Q[23]~reg0 {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.127 ns" { D1[23] Q[23]~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.127 ns" { D1[23] {} D1[23]~out0 {} Q[23]~reg0 {} } { 0.000ns 0.000ns 5.045ns } { 0.000ns 1.475ns 0.607ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "125 " "Info: Peak virtual memory: 125 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed May 27 11:54:56 2009 " "Info: Processing ended: Wed May 27 11:54:56 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}