adder.vhd

来自「本设计是用32位的并行全加器的,可以实现浮点运算!」· VHDL 代码 · 共 25 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY ADDER IS
PORT(
	D1  : IN SIGNED(31 DOWNTO 0);
	D2  : IN SIGNED(31 DOWNTO 0);
	Q   : OUT SIGNED(31 DOWNTO 0);
	ENABLE : IN STD_LOGIC);
END ADDER;

ARCHITECTURE BEHAVE OF ADDER IS
BEGIN
	PROCESS(ENABLE)
--	VARIABLE A,B : STD_LOGIC_VECTOR(12 DOWNTO 0);
	BEGIN
	--	A:='0'&D1;
	--	B:='0'&D2;
		IF ENABLE ='1' THEN
			Q<=D1+D2;
		END IF;
	END PROCESS;
END BEHAVE;