adder.flow.rpt

本设计是用32位的并行全加器的,可以实现浮点运算!

Flow report for ADDER
Wed May 27 11:54:56 2009
Quartus II Version 8.0 Build 215 05/29/2008 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Non-Default Global Settings
  5. Flow Elapsed Time
  6. Flow Log



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------+
; Flow Summary                                                       ;
+--------------------------+-----------------------------------------+
; Flow Status              ; Successful - Wed May 27 11:54:56 2009   ;
; Quartus II Version       ; 8.0 Build 215 05/29/2008 SJ Web Edition ;
; Revision Name            ; ADDER                                   ;
; Top-level Entity Name    ; ADDER                                   ;
; Family                   ; Cyclone                                 ;
; Device                   ; EP1C6Q240C8                             ;
; Timing Models            ; Final                                   ;
; Met timing requirements  ; Yes                                     ;
; Total logic elements     ; 32 / 5,980 ( < 1 % )                    ;
; Total pins               ; 97 / 185 ( 52 % )                       ;
; Total virtual pins       ; 0                                       ;
; Total memory bits        ; 0 / 92,160 ( 0 % )                      ;
; DSP block 9-bit elements ; N/A until Partition Merge               ;
; Total PLLs               ; 0 / 2 ( 0 % )                           ;
; Total DLLs               ; N/A until Partition Merge               ;
+--------------------------+-----------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 05/27/2009 11:54:44 ;
; Main task         ; Compilation         ;
; Revision Name     ; ADDER               ;
+-------------------+---------------------+


+--------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings                                                                             ;
+------------------------------------+------------------------------+---------------+-------------+------------+
; Assignment Name                    ; Value                        ; Default Value ; Entity Name ; Section Id ;
+------------------------------------+------------------------------+---------------+-------------+------------+
; COMPILER_SIGNATURE_ID              ; 964758874831.124339648402884 ; --            ; --          ; --         ;
; MAX_CORE_JUNCTION_TEMP             ; 85                           ; --            ; --          ; --         ;
; MIN_CORE_JUNCTION_TEMP             ; 0                            ; --            ; --          ; --         ;
; PARTITION_COLOR                    ; 14622752                     ; --            ; --          ; Top        ;
; PARTITION_NETLIST_TYPE             ; SOURCE                       ; --            ; --          ; Top        ;
; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off                          ; --            ; --          ; eda_palace ;
+------------------------------------+------------------------------+---------------+-------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time                                                                                                           ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name             ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis    ; 00:00:02     ; 1.0                     ; 175 MB              ; 00:00:02                           ;
; Fitter                  ; 00:00:03     ; 1.0                     ; 171 MB              ; 00:00:03                           ;
; Assembler               ; 00:00:01     ; 1.0                     ; 149 MB              ; 00:00:01                           ;
; Classic Timing Analyzer ; 00:00:00     ; 1.0                     ; 113 MB              ; 00:00:00                           ;
; Total                   ; 00:00:06     ; --                      ; --                  ; 00:00:06                           ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off ADDER -c ADDER
quartus_fit --read_settings_files=off --write_settings_files=off ADDER -c ADDER
quartus_asm --read_settings_files=off --write_settings_files=off ADDER -c ADDER
quartus_tan --read_settings_files=off --write_settings_files=off ADDER -c ADDER --timing_analysis_only