adder.map.summary

本设计是用32位的并行全加器的,可以实现浮点运算!

Analysis & Synthesis Status : Successful - Wed May 27 11:54:46 2009
Quartus II Version : 8.0 Build 215 05/29/2008 SJ Web Edition
Revision Name : ADDER
Top-level Entity Name : ADDER
Family : Cyclone
Total logic elements : 32
Total pins : 97
Total virtual pins : 0
Total memory bits : 0
DSP block 9-bit elements : N/A until Partition Merge
Total PLLs : 0
Total DLLs : N/A until Partition Merge