adder.tan.rpt

本设计是用32位的并行全加器的,可以实现浮点运算!

Classic Timing Analyzer report for ADDER
Wed May 27 11:54:56 2009
Quartus II Version 8.0 Build 215 05/29/2008 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. tsu
  6. tco
  7. th
  8. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                             ;
+------------------------------+-------+---------------+-------------+------------+------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From       ; To         ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------------+------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 9.027 ns    ; D2[19]     ; Q[31]~reg0 ; --         ; ENABLE   ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 9.606 ns    ; Q[28]~reg0 ; Q[28]      ; ENABLE     ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; -4.158 ns   ; D1[23]     ; Q[23]~reg0 ; --         ; ENABLE   ; 0            ;
; Total number of failed paths ;       ;               ;             ;            ;            ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+------------+------------+------------+----------+--------------+


+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                           ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                              ; Setting            ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                         ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;    ;             ;
; Minimum Core Junction Temperature                                   ; 0                  ;      ;    ;             ;
; Maximum Core Junction Temperature                                   ; 85                 ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; Off                ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; ENABLE          ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------+
; tsu                                                                                                                                         ;
+-----------------------------------------+-----------------------------------------------------+------------+--------+------------+----------+
; Slack                                   ; Required tsu                                        ; Actual tsu ; From   ; To         ; To Clock ;
+-----------------------------------------+-----------------------------------------------------+------------+--------+------------+----------+
; N/A                                     ; None                                                ; 9.027 ns   ; D2[19] ; Q[31]~reg0 ; ENABLE   ;
; N/A                                     ; None                                                ; 8.950 ns   ; D2[19] ; Q[26]~reg0 ; ENABLE   ;
; N/A                                     ; None                                                ; 8.950 ns   ; D2[19] ; Q[27]~reg0 ; ENABLE   ;
; N/A                                     ; None                                                ; 8.950 ns   ; D2[19] ; Q[28]~reg0 ; ENABLE   ;
; N/A                                     ; None                                                ; 8.950 ns   ; D2[19] ; Q[29]~reg0 ; ENABLE   ;
; N/A                                     ; None                                                ; 8.950 ns   ; D2[19] ; Q[30]~reg0 ; ENABLE   ;
; N/A                                     ; None                                                ; 8.916 ns   ; D2[8]  ; Q[31]~reg0 ; ENABLE   ;
; N/A                                     ; None                                                ; 8.858 ns   ; D2[24] ; Q[31]~reg0 ; ENABLE   ;
; N/A                                     ; None                                                ; 8.839 ns   ; D2[8]  ; Q[26]~reg0 ; ENABLE   ;