adder.pin

本设计是用32位的并行全加器的,可以实现浮点运算!

 -- Copyright (C) 1991-2008 Altera Corporation
 -- Your use of Altera Corporation's design tools, logic functions 
 -- and other software and tools, and its AMPP partner logic 
 -- functions, and any output files from any of the foregoing 
 -- (including device programming or simulation files), and any 
 -- associated documentation or information are expressly subject 
 -- to the terms and conditions of the Altera Program License 
 -- Subscription Agreement, Altera MegaCore Function License 
 -- Agreement, or other applicable license agreement, including, 
 -- without limitation, that your use is for the sole purpose of 
 -- programming logic devices manufactured by Altera and sold by 
 -- Altera or its authorized distributors.  Please refer to the 
 -- applicable agreement for further details.
 -- 
 -- This is a Quartus II output file. It is for reporting purposes only, and is
 -- not intended for use as a Quartus II input file. This file cannot be used
 -- to make Quartus II pin assignments - for instructions on how to make pin
 -- assignments, please see Quartus II help.
 ---------------------------------------------------------------------------------



 ---------------------------------------------------------------------------------
 -- NC            : No Connect. This pin has no internal connection to the device.
 -- DNU           : Do Not Use. This pin MUST NOT be connected.
 -- VCCPGM        : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V or 3.0V depending on the needs of the configuration device.
 -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.5V).
 -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
 --                 of its bank.
 --					Bank 1:		3.3V
 --					Bank 2:		3.3V
 --					Bank 3:		3.3V
 --					Bank 4:		3.3V
 -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
 --					It can also be used to report unused dedicated pins. The connection
 --					on the board for unused dedicated pins depends on whether this will
 --					be used in a future design. One example is device migration. When
 --					using device migration, refer to the device pin-tables. If it is a
 --					GND pin in the pin table or if it will not be used in a future design
 --					for another purpose the it MUST be connected to GND. If it is an unused
 --					dedicated pin, then it can be connected to a valid signal on the board
 --					(low, high, or toggling) if that signal is required for a different
 --					revision of the design.
 -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
 --					This pin should be connected to GND. It may also be connected  to a
 --					valid signal  on the board  (low, high, or toggling)  if that signal
 --					is required for a different revision of the design.
 -- GND*          : Unused  I/O  pin.   For transceiver I/O banks (Bank 13, 14, 15, 16 and 17),
 --           	    connect each pin marked GND* either individually through a 10 kohm resistor
 --           	    to GND or tie all pins together and connect through a single 10 kohm resistor
 --           	    to GND.
 --           	    For non-transceiver I/O banks, connect each pin marked GND* directly to GND
 --           	    or leave it unconnected.
 -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
 -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
 -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
 -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
 -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
 ---------------------------------------------------------------------------------



 ---------------------------------------------------------------------------------
 -- Pin directions (input, output or bidir) are based on device operating in user mode.
 ---------------------------------------------------------------------------------

Quartus II Version 8.0 Build 215 05/29/2008 SJ Web Edition
CHIP  "ADDER"  ASSIGNED TO AN: EP1C6Q240C8

Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
-------------------------------------------------------------------------------------------------------------
Q[0]                         : 1         : output : 3.3-V LVTTL       :         : 1         : N              
D2[1]                        : 2         : input  : 3.3-V LVTTL       :         : 1         : N              
Q[5]                         : 3         : output : 3.3-V LVTTL       :         : 1         : N              
Q[4]                         : 4         : output : 3.3-V LVTTL       :         : 1         : N              
GND*                         : 5         :        :                   :         : 1         :                
GND*                         : 6         :        :                   :         : 1         :                
D2[28]                       : 7         : input  : 3.3-V LVTTL       :         : 1         : N              
D2[5]                        : 8         : input  : 3.3-V LVTTL       :         : 1         : N              
VCCIO1                       : 9         : power  :                   : 3.3V    : 1         :                
GND                          : 10        : gnd    :                   :         :           :                
D1[6]                        : 11        : input  : 3.3-V LVTTL       :         : 1         : N              
Q[14]                        : 12        : output : 3.3-V LVTTL       :         : 1         : N              
Q[26]                        : 13        : output : 3.3-V LVTTL       :         : 1         : N              
D1[31]                       : 14        : input  : 3.3-V LVTTL       :         : 1         : N              
Q[13]                        : 15        : output : 3.3-V LVTTL       :         : 1         : N              
Q[24]                        : 16        : output : 3.3-V LVTTL       :         : 1         : N              
D2[11]                       : 17        : input  : 3.3-V LVTTL       :         : 1         : N              
Q[18]                        : 18        : output : 3.3-V LVTTL       :         : 1         : N              
Q[1]                         : 19        : output : 3.3-V LVTTL       :         : 1         : N              
Q[10]                        : 20        : output : 3.3-V LVTTL       :         : 1         : N              
Q[23]                        : 21        : output : 3.3-V LVTTL       :         : 1         : N              
VCCIO1                       : 22        : power  :                   : 3.3V    : 1         :                
Q[9]                         : 23        : output : 3.3-V LVTTL       :         : 1         : N              
~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 24        : input  : 3.3-V LVTTL       :         : 1         : N              
DATA0                        : 25        : input  :                   :         : 1         :                
nCONFIG                      : 26        :        :                   :         : 1         :                
VCCA_PLL1                    : 27        : power  :                   : 1.5V    :           :                
GND+                         : 28        :        :                   :         : 1         :                
ENABLE                       : 29        : input  : 3.3-V LVTTL       :         : 1         : N              
GNDA_PLL1                    : 30        : gnd    :                   :         :           :                
GNDG_PLL1                    : 31        : gnd    :                   :         :           :                
nCEO                         : 32        :        :                   :         : 1         :                
nCE                          : 33        :        :                   :         : 1         :