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📄 s3c2440.s

📁 三星的arm9芯片S3C2440的启动代码
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              	GET 2440addr.inc
                GET 2440option.inc
                
                
                
Mode_USR        EQU     0x10
Mode_FIQ        EQU     0x11
Mode_IRQ        EQU     0x12
Mode_SVC        EQU     0x13
Mode_ABT        EQU     0x17
Mode_UND        EQU     0x1B
Mode_SYS        EQU     0x1F                

MODEMASK    EQU 	0x1f
NOINT       EQU 	0xc0

FIQ_Stack  EQU     (_STACK_BASEADDRESS-0x0)	    ;0x33ff8000 ~
IRQ_Stack  EQU     (_STACK_BASEADDRESS-0x1000)	;0x33ff7000 ~
ABT_Stack  EQU     (_STACK_BASEADDRESS-0x2000)  ;0x33ff6000 ~
UND_Stack  EQU     (_STACK_BASEADDRESS-0x2400)  ;0x33ff5c00 ~
SVC_Stack  EQU     (_STACK_BASEADDRESS-0x2800)  ;0x33ff5800 ~
USR_Stack  EQU     (_STACK_BASEADDRESS-0x3800)	;0x33ff4800 ~ 


 
                PRESERVE8
                AREA    STACK, NOINIT, READWRITE, ALIGN=3

__initial_sp    SPACE   0x5000

Stack_Top



                PRESERVE8
                AREA    RESET, CODE, READONLY
                ARM
    MACRO
$HandlerLabel HANDLER $HandleLabel

$HandlerLabel
	sub	sp,sp,#4       	    ;decrement sp(to store jump address)
	stmfd	sp!,{r0}        ;PUSH the work register to stack(lr does't push because it return to original address)
	ldr     r0,=$HandleLabel;load the address of HandleXXX to r0
	ldr     r0,[r0]         ;load the contents(service routine start address) of HandleXXX
	str     r0,[sp,#4]      ;store the contents(ISR) of HandleXXX to stack
	ldmfd   sp!,{r0,pc}     ;POP the work register and pc(jump to ISR)
	MEND


                ;IMPORT  ||Image$$ER_ROM1$$RO$$Length||
                ;IMPORT  ||Image$$RW_RAM1$$RW$$Length||



Vectors         B Reset_Handler         
                NOP;LDR     PC, Undef_Addr
                NOP;LDR     PC, SWI_Addr
                NOP;LDR     PC, PAbt_Addr
                NOP;LDR     PC, DAbt_Addr
                NOP;B .
                B HandlerIRQ;LDR     PC, IRQ_Addr
                NOP;LDR     PC, FIQ_Addr
                
HandlerIRQ      HANDLER HandleIRQ

IsrIRQ  
	sub	sp, sp, #4       ;reserved for PC
	stmfd	sp!, {r8-r9}
	
	ldr	r9, =INTOFFSET
	ldr	r9, [r9]
	ldr	r8, =HandleEINT0
	add	r8, r8,r9,lsl #2
	ldr	r8, [r8]
	str	r8, [sp,#8]
	ldmfd	sp!,{r8-r9,pc}


                IMPORT  main
                ;IMPORT  NandFlashInit
                ;IMPORT  Copymem
                ;IMPORT  Create_Page_Table
                ;IMPORT  Mmu_Init
R1_M    EQU	(1) 


	EXPORT	__ENTRY
__ENTRY	
Reset_Handler   
                mrc p15,0,r0,c1,c0,0
                bic r0,r0,#R1_M
                mcr p15,0,r0,c1,c0,0

                mrc p15,0,r0,c1,c0,0;Turn On ICcache
                orr r0,r0,#(5<<12)  ;Use Round-Robin
                mcr p15,0,r0,c1,c0,0
                  
                LDR	R0,=WTCON       ;watch dog disable 
            	LDR	R1,=0           ;0xff21-->Enable Watchdog  
            	STR	R1,[R0]   
                                
                LDR R0,=400         ;Set FCLK At 400M ;HCLK At 200M ;PCLK At 100M
                BL SetPll
                           
                BL MemSetUp         ;Init SDRAM
                
                BL InitStacks
                
                
            	ldr	r0,=HandleIRQ       ;This routine is needed
            	ldr	r1,=IsrIRQ          ;if there isn't 'subs pc,lr,#4' at 0x18, 0x1c
            	str	r1,[r0]
                                
                BL main
Loop
            b Loop
            


InitStacks
            	MRS	R0,CPSR
            	BIC	R0,R0,#MODEMASK
                
            	ORR	R1,R0,#Mode_UND|NOINT
            	MSR	cpsr_cxsf,R1		;UndefMode
            	LDR	SP,=UND_Stack
            	
            	ORR	R1,R0,#Mode_ABT|NOINT
            	MSR	cpsr_cxsf,R1		;AbortMode
            	LDR	SP,=ABT_Stack
            
            	ORR	R1,R0,#Mode_IRQ|NOINT
            	MSR	cpsr_cxsf,R1		;IRQMode
            	LDR	sp,=IRQ_Stack
                
            	ORR	R1,R0,#Mode_FIQ|NOINT
            	MSR	cpsr_cxsf,R1		;FIQMode
            	LDR	SP,=FIQ_Stack
            
                ;ORR	R1,R0,#Mode_USR|NOINT
            	;MSR	cpsr_cxsf,R1		;FIQMode
            	;LDR	SP,=USR_Stack
                
            	BIC	R0,R0,#MODEMASK|NOINT
            	ORR	R1,R0,#Mode_SVC
            	MSR	cpsr_cxsf,R1		;SVCMode
            	LDR	SP,=SVC_Stack
               
            	BX lr 
                
                EXPORT __initial_sp
               
MemSetUp
                LDR  R1,=BWSCON      
                ADRL R2,mem_cfg_val        
                ADD  R3,R1, #52             
b  
                LDR R4,[R2], #4          
                STR R4,[R1], #4            
                CMP R1,R3                 
                BNE b                          
                BX LR     

mem_cfg_val DCD 0x22000000,0x00000700,0x00000700,0x00000700,0x00000700,0x00000700,0x00000700,\
                0x00018005,0x00018005,0x008D2B7A,0x00000032,0x00000030,0x00000030       
                ; BWSCON; BANKCON0; BANKCON1; BANKCON2; BANKCON3; BANKCON4; BANKCON5;
                ; BANKCON6; BANKCON7; REFRESH; BANKSIZE; MRSRB6; MRSRB7         
            
steppingstone_to_sdram
                MOV R1, #0
                LDR R2, =0x30000000
                MOV R3, #4*1024
c  
                LDR R4, [R1],#4    
                STR R4, [R2],#4    
                CMP R1, R3          
                BNE c               
                BX LR            
 
                EXPORT SetPll
SetPll          ;Set Pll , DanWei M ,200M--500M ; R0 Save The Value , Mhz;
                SUB	SP,SP,#4       	  
            	STMFD SP!,{R0,R1}
                MOV R3,R0
                
                LDR	R0,=CLKCON 
            	LDR	R1,=0xfffffff0  ;All Clock is On	
            	STR	R1,[R0]
                
                ;LDR	R0,=UPLLCON     ;UPLL=48M	
            	;LDR	R1,=0x380A      
            	;STR	R1,[R0]
    
                ;SUB R3,R3,#16        ;M_MDIV=(Clk-16)/2
                ;MOV R1,R3,LSR #1
                ;LDR	R0,=MPLLCON      ;MPLL	
            	;MOV	R1,R1,LSL #12
                ;ORR R1,R1,#((1<<4)+2)     
            	;STR	R1,[R0] 
                
                LDR	R0,=MPLLCON
                LDR R1,=0x5c
            	MOV	R1,R1,LSL #12
                ORR R1,R1,#((1<<4)+1)  
            	STR	R1,[R0] 
               
       
                LDR	R0,=LOCKTIME
            	LDR	R1,=0x00ff00ff
            	STR	R1,[R0]
                ;400M  200M  100M
                LDR	R0,=CLKDIVN 	;0=1:1:1, 1=1:1:2, 2=1:2:2, 3=1:2:4, 4=1:4:4, 5=1:4:8, 6=1:3:3, 7=1:3:6.
            	LDR	R1,=5           ;FCLK:HCLK:PCLK=1:1:1	
            	STR	R1,[R0]
                
                
                MRC p15,0,R0,c1,c0,0 ;Turn to UnSync Mode
                ORR R0,R0,#(1<<30):OR:(1<<31)
               	MCR p15,0,R0,c1,c0,0

	            LDMFD SP!,{R1,R0}
                BX  LR
               
               
        EXPORT Mmu_Init
Mmu_Init   
       MOV R0, #0
       MCR p15,0,R0,c7,c7,0  ;Disable ICache And DCache
       
       MCR p15,0,R0,c7,c10,4
       MCR p15,0,R0,c8,c7,0  ;Disable ITLB,DTLB
       
       MOV R4,#0x30000000
       MCR p15,0,R4,c2,c0,0
       
       MOV R0,#0
       MCR p15,0,R0,c3,c0,0
       
       MRC p15,0,R0,c1,c0,0
       
       BIC R0,R0,#0x3000
       BIC R0,R0,#0x0300
       BIC R0,R0,#0x0087
       
       ORR R0,R0,#0x0002
       ORR R0,R0,#0x0004
       ORR R0,R0,#0x1000
       ORR R0,R0,#0x0001
       
       MCR p15,0,R0,c1,c0,0
       BX  LR
      
      

                PRESERVE8
                AREA    RamData, DATA, READWRITE
                ARM

        ^   _ISR_STARTADDRESS
HandleReset 	#   4
HandleUndef 	#   4
HandleSWI   	#   4
HandlePabort    #   4
HandleDabort    #   4
HandleReserved  #   4
HandleIRQ   	#   4
HandleFIQ   	#   4

HandleEINT0   	#   4
HandleEINT1   	#   4
HandleEINT2   	#   4
HandleEINT3   	#   4
HandleEINT4_7	#   4
HandleEINT8_23	#   4
HandleRSV6	#   4
HandleBATFLT   	#   4
HandleTICK   	#   4
HandleWDT	#   4
HandleTIMER0 	#   4
HandleTIMER1 	#   4
HandleTIMER2 	#   4
HandleTIMER3 	#   4
HandleTIMER4 	#   4
HandleUART2  	#   4
HandleLCD 	#   4
HandleDMA0	#   4
HandleDMA1	#   4
HandleDMA2	#   4
HandleDMA3	#   4
HandleMMC	#   4
HandleSPI0	#   4
HandleUART1	#   4
HandleRSV24	#   4
HandleUSBD	#   4
HandleUSBH	#   4
HandleIIC   	#   4
HandleUART0 	#   4
HandleSPI1 	#   4
HandleRTC 	#   4
HandleADC 	#   4               

        END

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