📄 os_cpu_a.lst
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ARM Macro Assembler Page 5
From interrupt level)
160 00000038 ; void OSIntCtxS
w(void)
161 00000038 ;
162 00000038 ; Notes: 1) OSIntCtxSw() is called by OSIntExit() whe
n it determines a context switch is needed as
163 00000038 ; the result of an interrupt. This functio
n simply triggers a PendSV exception which will
164 00000038 ; be handled when there are no more interru
pts active and interrupts are enabled.
165 00000038 ;*******************************************************
**************************************************
166 00000038
167 00000038 OSIntCtxSw
168 00000038 481A LDR R0, =NVIC_INT_CTRL ; Trigger th
e PendSV exception
(causes context swi
tch)
169 0000003A F04F 5180 LDR R1, =NVIC_PENDSVSET
170 0000003E 6001 STR R1, [R0]
171 00000040 4770 BX LR
172 00000042
173 00000042 ;*******************************************************
**************************************************
174 00000042 ; HANDLE PendSV
EXCEPTION
175 00000042 ; void OSPend
SV(void)
176 00000042 ;
177 00000042 ; Note(s) : 1) OSPendSV is used to cause a context switc
h. This is a recommended method for performing
178 00000042 ; context switches with Cortex-M3. This is
because the Cortex-M3 auto-saves half of the
179 00000042 ; processor context on any exception, and r
estores same on return from exception. So only
180 00000042 ; saving of R4-R11 is required and fixing u
p the stack pointers. Using the PendSV exception
181 00000042 ; this way means that context saving and re
storing is identical whether it is initiated from
182 00000042 ; a thread or occurs due to an interrupt or
exception.
183 00000042 ;
184 00000042 ; 2) Pseudo-code is:
185 00000042 ; a) Get the process SP, if 0 then skip (go
to d) the saving part (first context switch);
186 00000042 ; b) Save remaining regs r4-r11 on process
stack;
187 00000042 ; c) Save the process SP in its TCB, OSTCBC
ur->OSTCBStkPtr = SP;
188 00000042 ; d) Call OSTaskSwHook();
189 00000042 ; e) Get current high priority, OSPrioCur =
OSPrioHighRdy;
190 00000042 ; f) Get current ready thread TCB, OSTCBCur
= OSTCBHighRdy;
191 00000042 ; g) Get new process SP from TCB, SP = OSTC
BHighRdy->OSTCBStkPtr;
192 00000042 ; h) Restore R4-R11 from new process stack;
193 00000042 ; i) Perform exception return which will re
ARM Macro Assembler Page 6
store remaining context.
194 00000042 ;
195 00000042 ; 3) On entry into OSPendSV handler:
196 00000042 ; a) The following have been saved on the p
rocess stack (by processor):
197 00000042 ; xPSR, PC, LR, R12, R0-R3
198 00000042 ; b) Processor mode is switched to Handler
mode (from Thread mode)
199 00000042 ; c) Stack is Main stack (switched from Pro
cess stack)
200 00000042 ; d) OSTCBCur points to the OS_TCB of
the task to suspend
201 00000042 ; OSTCBHighRdy points to the OS_TCB of
the task to resume
202 00000042 ;
203 00000042 ; 4) Since OSPendSV is set to lowest priority
in the system (by OSStartHighRdy() above), we
204 00000042 ; know that it will only be run when no oth
er exception or interrupt is active, and
205 00000042 ; therefore safe to assume that context bei
ng switched out was using the process stack (PSP).
206 00000042 ;*******************************************************
**************************************************
207 00000042
208 00000042 PendSV_Handler
209 00000042 F3EF 8009 MRS R0, PSP ; PSP is process st
ack pointer
210 00000046 B128 CBZ R0, OSPendSV_nosave ; skip regi
ster save the first
time
211 00000048
212 00000048 3820 SUBS R0, R0, #0x20 ; save remaining
regs r4-11 on proce
ss stack
213 0000004A E880 0FF0 STM R0, {R4-R11}
214 0000004E
215 0000004E 4912 LDR R1, __OS_TCBCur ; OSTCBCur->OST
CBStkPtr = SP;
216 00000050 6809 LDR R1, [R1]
217 00000052 6008 STR R0, [R1] ; R0 is SP of proce
ss being switched o
ut
218 00000054
219 00000054 ; at this point, entire context of process has been save
d
220 00000054 OSPendSV_nosave
221 00000054 B500 PUSH {R14} ; need to save LR e
xc_return value
222 00000056 480A LDR R0, __OS_TaskSwHook
; OSTaskSwHook();
223 00000058 4780 BLX R0
224 0000005A F85D EB04 POP {R14}
225 0000005E
226 0000005E 480B LDR R0, __OS_PrioCur ; OSPrioCur =
OSPrioHighRdy;
227 00000060 490B LDR R1, __OS_PrioHighRdy
228 00000062 780A LDRB R2, [R1]
229 00000064 7002 STRB R2, [R0]
230 00000066
ARM Macro Assembler Page 7
231 00000066 480C LDR R0, __OS_TCBCur ; OSTCBCur = O
STCBHighRdy;
232 00000068 490C LDR R1, __OS_TCBHighRdy
233 0000006A 680A LDR R2, [R1]
234 0000006C 6002 STR R2, [R0]
235 0000006E
236 0000006E 6810 LDR R0, [R2] ; R0 is new process
SP; SP = OSTCBHigh
Rdy->OSTCBStkPtr;
237 00000070 E890 0FF0 LDM R0, {R4-R11} ; restore r4-11 fr
om new process stac
k
238 00000074 3020 ADDS R0, R0, #0x20
239 00000076 F380 8809 MSR PSP, R0 ; load PSP with new
process SP
240 0000007A F04E 0E04 ORR LR, LR, #0x04 ; ensure exceptio
n return uses proce
ss stack
241 0000007E 4770 BX LR ; exception return
will restore remain
ing context
242 00000080
243 00000080
244 00000080 ;*******************************************************
**************************************************
245 00000080 ; POINTERS TO VARIAB
LES
246 00000080 ;*******************************************************
**************************************************
247 00000080
248 00000080 __OS_TaskSwHook
249 00000080 00000000 DCD OSTaskSwHook
250 00000084
251 00000084 __OS_IntExit
252 00000084 00000000 DCD OSIntExit
253 00000088
254 00000088 __OS_IntNesting
255 00000088 00000000 DCD OSIntNesting
256 0000008C
257 0000008C __OS_PrioCur
258 0000008C 00000000 DCD OSPrioCur
259 00000090
260 00000090 __OS_PrioHighRdy
261 00000090 00000000 DCD OSPrioHighRdy
262 00000094
263 00000094 __OS_Running
264 00000094 00000000 DCD OSRunning
265 00000098
266 00000098 __OS_TCBCur
267 00000098 00000000 DCD OSTCBCur
268 0000009C
269 0000009C __OS_TCBHighRdy
270 0000009C 00000000 DCD OSTCBHighRdy
271 000000A0
272 000000A0 END
E000ED20
E000ED04
Command Line: --debug --xref --device=DARMSTM --apcs=interwork -o.\os_cpu_a.o -
IC:\Keil\ARM\INC\ST\STM32F10x --list=.\os_cpu_a.lst ..\CortexM3\os_cpu_a.asm
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Relocatable symbols
.text 00000000
Symbol: .text
Definitions
At line 56 in file ..\CortexM3\os_cpu_a.asm
Uses
None
Comment: .text unused
OSCtxSw 0000002E
Symbol: OSCtxSw
Definitions
At line 152 in file ..\CortexM3\os_cpu_a.asm
Uses
At line 39 in file ..\CortexM3\os_cpu_a.asm
Comment: OSCtxSw used once
OSIntCtxSw 00000038
Symbol: OSIntCtxSw
Definitions
At line 167 in file ..\CortexM3\os_cpu_a.asm
Uses
At line 40 in file ..\CortexM3\os_cpu_a.asm
Comment: OSIntCtxSw used once
OSPendSV_nosave 00000054
Symbol: OSPendSV_nosave
Definitions
At line 220 in file ..\CortexM3\os_cpu_a.asm
Uses
At line 210 in file ..\CortexM3\os_cpu_a.asm
Comment: OSPendSV_nosave used once
OSStartHang 0000002C
Symbol: OSStartHang
Definitions
At line 140 in file ..\CortexM3\os_cpu_a.asm
Uses
At line 141 in file ..\CortexM3\os_cpu_a.asm
Comment: OSStartHang used once
OSStartHighRdy 0000000E
Symbol: OSStartHighRdy
Definitions
At line 122 in file ..\CortexM3\os_cpu_a.asm
Uses
At line 38 in file ..\CortexM3\os_cpu_a.asm
Comment: OSStartHighRdy used once
OS_CPU_SR_Restore 00000008
Symbol: OS_CPU_SR_Restore
Definitions
At line 102 in file ..\CortexM3\os_cpu_a.asm
Uses
At line 37 in file ..\CortexM3\os_cpu_a.asm
Comment: OS_CPU_SR_Restore used once
OS_CPU_SR_Save 00000000
Symbol: OS_CPU_SR_Save
ARM Macro Assembler Page 2 Alphabetic symbol ordering
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