📄 os_cpu_a.lst
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ARM Macro Assembler Page 1
1 00000000 ;*******************************************************
*************************************************
2 00000000 ; uC/OS-II
3 00000000 ; The Real-Time
Kernel
4 00000000 ;
5 00000000 ; (c) Copyright 1992-2006,
Micrium, Weston, FL
6 00000000 ; All Rights Re
served
7 00000000 ;
8 00000000 ; Generic ARM
Port
9 00000000 ;
10 00000000 ; File : OS_CPU_A.ASM
11 00000000 ; Version : V2.86
12 00000000 ; By : Jean J. Labrosse
13 00000000 ;
14 00000000 ; For : ARMv7M Cortex-M3
15 00000000 ; Mode : Thumb2
16 00000000 ; Toolchain : RealView Development Suite
17 00000000 ; RealView Microcontroller Development Kit (
MDK)
18 00000000 ; ARM Developer Suite (ADS)
19 00000000 ; Keil uVision
20 00000000 ;*******************************************************
*************************************************
21 00000000
22 00000000 ;*******************************************************
*************************************************
23 00000000 ; PUBLIC FUNCT
IONS
24 00000000 ;*******************************************************
*************************************************
25 00000000
26 00000000 EXTERN OSRunning ; External referenc
es
27 00000000 EXTERN OSPrioCur
28 00000000 EXTERN OSPrioHighRdy
29 00000000 EXTERN OSTCBCur
30 00000000 EXTERN OSTCBHighRdy
31 00000000 EXTERN OSIntNesting
32 00000000 EXTERN OSIntExit
33 00000000 EXTERN OSTaskSwHook
34 00000000
35 00000000
36 00000000 EXPORT OS_CPU_SR_Save ; Functions decl
ared in this file
37 00000000 EXPORT OS_CPU_SR_Restore
38 00000000 EXPORT OSStartHighRdy
39 00000000 EXPORT OSCtxSw
40 00000000 EXPORT OSIntCtxSw
41 00000000 EXPORT PendSV_Handler
42 00000000
43 00000000 ;*******************************************************
*************************************************
44 00000000 ; EQUATES
ARM Macro Assembler Page 2
45 00000000 ;*******************************************************
*************************************************
46 00000000
47 00000000 E000ED04
NVIC_INT_CTRL
EQU 0xE000ED04 ; Interrupt control
state register
48 00000000 E000ED20
NVIC_SYSPRI2
EQU 0xE000ED20 ; System priority r
egister (2)
49 00000000 00000000
NVIC_PENDSV_PRI
EQU 0x00 ; PendSV priority v
alue (highest)
50 00000000 10000000
NVIC_PENDSVSET
EQU 0x10000000 ; Value to trigger
PendSV exception
51 00000000
52 00000000 ;*******************************************************
*************************************************
53 00000000 ; CODE GENERATION D
IRECTIVES
54 00000000 ;*******************************************************
*************************************************
55 00000000
56 00000000 AREA |.text|, CODE, READONLY, ALIGN=
2
57 00000000 THUMB
58 00000000 REQUIRE8
59 00000000 PRESERVE8
60 00000000
61 00000000 ;*******************************************************
**************************************************
62 00000000 ; CRITICAL SECTION MET
HOD 3 FUNCTIONS
63 00000000 ;
64 00000000 ; Description: Disable/Enable interrupts by preserving t
he state of interrupts. Generally speaking you
65 00000000 ; would store the state of the interrupt di
sable flag in the local variable 'cpu_sr' and then
66 00000000 ; disable interrupts. 'cpu_sr' is allocate
d in all of uC/OS-II's functions that need to
67 00000000 ; disable interrupts. You would restore th
e interrupt disable state by copying back 'cpu_sr'
68 00000000 ; into the CPU's status register.
69 00000000 ;
70 00000000 ; Prototypes : OS_CPU_SR OS_CPU_SR_Save(void);
71 00000000 ; void OS_CPU_SR_Restore(OS_CPU_S
R cpu_sr);
72 00000000 ;
73 00000000 ;
74 00000000 ; Note(s) : 1) These functions are used in general li
ke this:
75 00000000 ;
76 00000000 ; void Task (void *p_arg)
77 00000000 ; {
78 00000000 ; #if OS_CRITICAL_METHOD == 3 /
ARM Macro Assembler Page 3
* Allocate storage for CPU status register */
79 00000000 ; OS_CPU_SR cpu_sr;
80 00000000 ; #endif
81 00000000 ;
82 00000000 ; :
83 00000000 ; :
84 00000000 ; OS_ENTER_CRITICAL(); /
* cpu_sr = OS_CPU_SaveSR(); */
85 00000000 ; :
86 00000000 ; :
87 00000000 ; OS_EXIT_CRITICAL(); /
* OS_CPU_RestoreSR(cpu_sr); */
88 00000000 ; :
89 00000000 ; :
90 00000000 ; }
91 00000000 ;
92 00000000 ; 2) OS_CPU_SaveSR() is implemented as reco
mmended by Atmel's application note:
93 00000000 ;
94 00000000 ; (N/A for Cortex-M3) "Disabling Interrupt
s at Processor Level"
95 00000000 ;*******************************************************
**************************************************
96 00000000
97 00000000 OS_CPU_SR_Save
98 00000000 F3EF 8010 MRS R0, PRIMASK ; Set prio int mask
to mask all (excep
t faults)
99 00000004 B672 CPSID I
100 00000006 4770 BX LR
101 00000008
102 00000008 OS_CPU_SR_Restore
103 00000008 F380 8810 MSR PRIMASK, R0
104 0000000C 4770 BX LR
105 0000000E
106 0000000E
107 0000000E ;*******************************************************
**************************************************
108 0000000E ; START MULTITA
SKING
109 0000000E ; void OSStartHigh
Rdy(void)
110 0000000E ;
111 0000000E ; Note(s) : 1) This function triggers a PendSV exception
(essentially, causes a context switch) to cause
112 0000000E ; the first task to start.
113 0000000E ;
114 0000000E ; 2) OSStartHighRdy() MUST:
115 0000000E ; a) Setup PendSV exception priority to low
est;
116 0000000E ; b) Set initial PSP to 0, to tell context
switcher this is first run;
117 0000000E ; c) Set OSRunning to TRUE;
118 0000000E ; d) Trigger PendSV exception;
119 0000000E ; e) Enable interrupts (tasks will run with
interrupts enabled).
120 0000000E ;*******************************************************
**************************************************
121 0000000E
ARM Macro Assembler Page 4
122 0000000E OSStartHighRdy
123 0000000E 4824 LDR R0, =NVIC_SYSPRI2 ; Set the Pen
dSV exception prior
ity
124 00000010 F04F 0100 LDR R1, =NVIC_PENDSV_PRI
125 00000014 7001 STRB R1, [R0]
126 00000016
127 00000016 2000 MOVS R0, #0 ; Set the PSP to 0
for initial context
switch call
128 00000018 F380 8809 MSR PSP, R0
129 0000001C
130 0000001C 481D LDR R0, __OS_Running
; OSRunning = TRUE
131 0000001E 2101 MOVS R1, #1
132 00000020 7001 STRB R1, [R0]
133 00000022
134 00000022 4820 LDR R0, =NVIC_INT_CTRL ; Trigger th
e PendSV exception
(causes context swi
tch)
135 00000024 F04F 5180 LDR R1, =NVIC_PENDSVSET
136 00000028 6001 STR R1, [R0]
137 0000002A
138 0000002A B662 CPSIE I ; Enable interrupts
at processor level
139 0000002C
140 0000002C OSStartHang
141 0000002C E7FE B OSStartHang ; Should never get
here
142 0000002E
143 0000002E
144 0000002E ;*******************************************************
**************************************************
145 0000002E ; PERFORM A CONTEXT SWITCH
(From task level)
146 0000002E ; void OSCtxSw
(void)
147 0000002E ;
148 0000002E ; Note(s) : 1) OSCtxSw() is called when OS wants to perf
orm a task context switch. This function
149 0000002E ; triggers the PendSV exception which is wh
ere the real work is done.
150 0000002E ;*******************************************************
**************************************************
151 0000002E
152 0000002E OSCtxSw
153 0000002E 481D LDR R0, =NVIC_INT_CTRL ; Trigger th
e PendSV exception
(causes context swi
tch)
154 00000030 F04F 5180 LDR R1, =NVIC_PENDSVSET
155 00000034 6001 STR R1, [R0]
156 00000036 4770 BX LR
157 00000038
158 00000038 ;*******************************************************
**************************************************
159 00000038 ; PERFORM A CONTEXT SWITCH (
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