📄 f2812_reg.h
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union PIEIER_REG PIEIER11; // PIE INT11 IER register
union PIEIFR_REG PIEIFR11; // PIE INT11 IFR register
union PIEIER_REG PIEIER12; // PIE INT12 IER register
union PIEIFR_REG PIEIFR12; // PIE INT12 IFR register
};
//________________________________________________________________________________________________________
struct PIE_VECT_TABLE {
// Reset is never fetched from this table.
// It will always be fetched from 0x3FFFC0 in either
// boot ROM or XINTF Zone 7 depending on the state of
// the XMP/MC input signal. On the F2810 it is always
// fetched from boot ROM.
PINT PIE1_RESERVED;
PINT PIE2_RESERVED;
PINT PIE3_RESERVED;
PINT PIE4_RESERVED;
PINT PIE5_RESERVED;
PINT PIE6_RESERVED;
PINT PIE7_RESERVED;
PINT PIE8_RESERVED;
PINT PIE9_RESERVED;
PINT PIE10_RESERVED;
PINT PIE11_RESERVED;
PINT PIE12_RESERVED;
PINT PIE13_RESERVED;
// Non-Peripheral Interrupts:
PINT XINT13; // XINT13
PINT TINT2; // CPU-Timer2
PINT DATALOG; // Datalogging interrupt
PINT RTOSINT; // RTOS interrupt
PINT EMUINT; // Emulation interrupt
PINT XNMI; // Non-maskable interrupt
PINT ILLEGAL; // Illegal operation TRAP
PINT USER1; // User Defined trap 1
PINT USER2; // User Defined trap 2
PINT USER3; // User Defined trap 3
PINT USER4; // User Defined trap 4
PINT USER5; // User Defined trap 5
PINT USER6; // User Defined trap 6
PINT USER7; // User Defined trap 7
PINT USER8; // User Defined trap 8
PINT USER9; // User Defined trap 9
PINT USER10; // User Defined trap 10
PINT USER11; // User Defined trap 11
PINT USER12; // User Defined trap 12
// Group 1 PIE Peripheral Vectors:
PINT PDPINTA; // EV-A
PINT PDPINTB; // EV-B
PINT rsvd1_3;
PINT XINT1;
PINT XINT2;
PINT ADCINT; // ADC
PINT TINT0; // Timer 0
PINT WAKEINT; // WD
// Group 2 PIE Peripheral Vectors:
PINT CMP1INT; // EV-A
PINT CMP2INT; // EV-A
PINT CMP3INT; // EV-A
PINT T1PINT; // EV-A
PINT T1CINT; // EV-A
PINT T1UFINT; // EV-A
PINT T1OFINT; // EV-A
PINT rsvd2_8;
// Group 3 PIE Peripheral Vectors:
PINT T2PINT; // EV-A
PINT T2CINT; // EV-A
PINT T2UFINT; // EV-A
PINT T2OFINT; // EV-A
PINT CAPINT1; // EV-A
PINT CAPINT2; // EV-A
PINT CAPINT3; // EV-A
PINT rsvd3_8;
// Group 4 PIE Peripheral Vectors:
PINT CMP4INT; // EV-B
PINT CMP5INT; // EV-B
PINT CMP6INT; // EV-B
PINT T3PINT; // EV-B
PINT T3CINT; // EV-B
PINT T3UFINT; // EV-B
PINT T3OFINT; // EV-B
PINT rsvd4_8;
// Group 5 PIE Peripheral Vectors:
PINT T4PINT; // EV-B
PINT T4CINT; // EV-B
PINT T4UFINT; // EV-B
PINT T4OFINT; // EV-B
PINT CAPINT4; // EV-B
PINT CAPINT5; // EV-B
PINT CAPINT6; // EV-B
PINT rsvd5_8;
// Group 6 PIE Peripheral Vectors:
PINT SPIRXINTA; // SPI-A
PINT SPITXINTA; // SPI-A
PINT rsvd6_3;
PINT rsvd6_4;
PINT MRINTA; // McBSP-A
PINT MXINTA; // McBSP-A
PINT rsvd6_7;
PINT rsvd6_8;
// Group 7 PIE Peripheral Vectors:
PINT rsvd7_1;
PINT rsvd7_2;
PINT rsvd7_3;
PINT rsvd7_4;
PINT rsvd7_5;
PINT rsvd7_6;
PINT rsvd7_7;
PINT rsvd7_8;
// Group 8 PIE Peripheral Vectors:
PINT rsvd8_1;
PINT rsvd8_2;
PINT rsvd8_3;
PINT rsvd8_4;
PINT rsvd8_5;
PINT rsvd8_6;
PINT rsvd8_7;
PINT rsvd8_8;
// Group 9 PIE Peripheral Vectors:
PINT RXAINT; // SCI-A
PINT TXAINT; // SCI-A
PINT RXBINT; // SCI-B
PINT TXBINT; // SCI-B
PINT ECAN0INTA; // eCAN
PINT ECAN1INTA; // eCAN
PINT rsvd9_7;
PINT rsvd9_8;
// Group 10 PIE Peripheral Vectors:
PINT rsvd10_1;
PINT rsvd10_2;
PINT rsvd10_3;
PINT rsvd10_4;
PINT rsvd10_5;
PINT rsvd10_6;
PINT rsvd10_7;
PINT rsvd10_8;
// Group 11 PIE Peripheral Vectors:
PINT rsvd11_1;
PINT rsvd11_2;
PINT rsvd11_3;
PINT rsvd11_4;
PINT rsvd11_5;
PINT rsvd11_6;
PINT rsvd11_7;
PINT rsvd11_8;
// Group 12 PIE Peripheral Vectors:
PINT rsvd12_1;
PINT rsvd12_2;
PINT rsvd12_3;
PINT rsvd12_4;
PINT rsvd12_5;
PINT rsvd12_6;
PINT rsvd12_7;
PINT rsvd12_8;
};
//__________________________________________________________________________________________________
// XINTF timing register bit definitions:
struct XTIMING_BITS { // bits description
Uint16 XWRTRAIL:2; // 1:0 Write access trail timing
Uint16 XWRACTIVE:3; // 4:2 Write access active timing
Uint16 XWRLEAD:2; // 6:5 Write access lead timing
Uint16 XRDTRAIL:2; // 8:7 Read access trail timing
Uint16 XRDACTIVE:3; // 11:9 Read access active timing
Uint16 XRDLEAD:2; // 13:12 Read access lead timing
Uint16 USEREADY:1; // 14 Extend access using HW waitstates
Uint16 READYMODE:1; // 15 Ready mode
Uint16 XSIZE:2; // 17:16 XINTF bus width - must be written as 11b
Uint16 rsvd1:4; // 21:18 reserved
Uint16 X2TIMING:1; // 22 Double lead/active/trail timing
Uint16 rsvd3:9; // 31:23 reserved
};
union XTIMING_REG {
Uint32 all;
struct XTIMING_BITS bit;
};
// XINTF control register bit definitions:
struct XINTCNF2_BITS { // bits description
Uint16 WRBUFF:2; // 1:0 Write buffer depth
Uint16 CLKMODE:1; // 2 Ratio for XCLKOUT with respect to XTIMCLK
Uint16 CLKOFF:1; // 3 Disable XCLKOUT
Uint16 rsvd1:2; // 5:4 reserved
Uint16 WLEVEL:2; // 7:6 Current level of the write buffer
Uint16 MPNMC:1; // 8 Micro-processor/micro-computer mode
Uint16 HOLD:1; // 9 Hold enable/disable
Uint16 HOLDS:1; // 10 Current state of HOLDn input
Uint16 HOLDAS:1; // 11 Current state of HOLDAn output
Uint16 rsvd2:4; // 15:12 reserved
Uint16 XTIMCLK:3; // 18:16 Ratio for XTIMCLK
Uint16 rsvd3:13; // 31:19 reserved
};
union XINTCNF2_REG {
Uint32 all;
struct XINTCNF2_BITS bit;
};
// XINTF bank switching register bit definitions:
struct XBANK_BITS { // bits description
Uint16 BANK:3; // 2:0 Zone for which banking is enabled
Uint16 BCYC:3; // 5:3 XTIMCLK cycles to add
Uint16 rsvd:10; // 15:6 reserved
};
union XBANK_REG {
Uint16 all;
struct XBANK_BITS bit;
};
//---------------------------------------------------------------------------
// XINTF Register File:
//
struct XINTF_REGS {
union XTIMING_REG XTIMING0;
union XTIMING_REG XTIMING1;
union XTIMING_REG XTIMING2;
Uint32 rsvd1[3];
union XTIMING_REG XTIMING6;
union XTIMING_REG XTIMING7;
Uint32 rsvd2[2];
union XINTCNF2_REG XINTCNF2;
Uint32 rsvd3;
union XBANK_REG XBANK;
Uint16 rsvd4;
Uint16 XREVISION;
Uint16 rsvd5[5];
};
#define SysCtrlRegs ((volatile struct SYS_CTRL_REGS *)(0x007010)) // System control registers
#define PieCtrlRegs ((volatile struct PIE_CTRL_REGS *)(0x000CE0)) // PIE control registers
#define PieVectTable (( struct PIE_VECT_TABLE *)(0x000D00)) // PIE Vector Table
#define XintfRegs ((volatile struct XINTF_REGS *)(0x000B20)) // external interface registers
//Uint16 *P_sram=(Uint16 *)0x100000;
//Uint16 *P_cpld=(Uint16 *)0x002000;
//Uint16 *P_ext=(Uint16 *)0x080000;
#define P_sram ((volatile Uint16 *)(0x100000))
#define P_cpld ((volatile Uint16 *)(0x002000))
#define P_ext ((volatile Uint16 *)(0x080000))
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif //__F2812_REG_H__
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