📄 f2812_init.c
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// -----------------------------------------------------------
// PIE Group 9 - MUXed into CPU INT9
// -----------------------------------------------------------
// INT9.1
interrupt void SCIRXINTA_ISR(void) // SCI-A
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT9.2
interrupt void SCITXINTA_ISR(void) // SCI-A
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT9.3
interrupt void SCIRXINTB_ISR(void) // SCI-B
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT9.4
interrupt void SCITXINTB_ISR(void) // SCI-B
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT9.5
interrupt void ECAN0INTA_ISR(void) // eCAN-A
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// INT9.6
interrupt void ECAN1INTA_ISR(void) // eCAN-A
{
// Insert ISR Code here
// To receive more interrupts from this PIE group, acknowledge this interrupt
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP9;
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm (" ESTOP0");
for(;;);
}
// -----------------------------------------------------------
// PIE Group 10 - MUXed into CPU INT10
// -----------------------------------------------------------
// INT10.1 - Reserved
// INT10.2 - Reserved
// INT10.3 - Reserved
// INT10.4 - Reserved
// INT10.5 - Reserved
// INT10.6 - Reserved
// INT10.7 - Reserved
// INT10.8 - Reserved
// -----------------------------------------------------------
// PIE Group 11 - MUXed into CPU INT11
// -----------------------------------------------------------
// INT11.1 - Reserved
// INT11.2 - Reserved
// INT11.3 - Reserved
// INT11.4 - Reserved
// INT11.5 - Reserved
// INT11.6 - Reserved
// INT11.7 - Reserved
// INT11.8 - Reserved
// -----------------------------------------------------------
// PIE Group 12 - MUXed into CPU INT12
// -----------------------------------------------------------
// INT12.1 - Reserved
// INT12.2 - Reserved
// INT12.3 - Reserved
// INT12.4 - Reserved
// INT12.5 - Reserved
// INT12.6 - Reserved
// INT12.7 - Reserved
// INT12.8 - Reserved
//---------------------------------------------------------------------------
// Catch All Default ISRs:
//
interrupt void EMPTY_ISR(void) // Empty ISR - only does a return.
{
}
interrupt void PIE_RESERVED(void) // Reserved space. For test.
{
asm (" ESTOP0");
for(;;);
}
interrupt void rsvd_ISR(void) // For test
{
asm (" ESTOP0");
for(;;);
}
const struct PIE_VECT_TABLE PieVectTableInit = {
PIE_RESERVED, // Reserved space
PIE_RESERVED,
PIE_RESERVED,
PIE_RESERVED,
PIE_RESERVED,
PIE_RESERVED,
PIE_RESERVED,
PIE_RESERVED,
PIE_RESERVED,
PIE_RESERVED,
PIE_RESERVED,
PIE_RESERVED,
PIE_RESERVED,
// Non-Peripheral Interrupts
INT13_ISR, // XINT13 or CPU-Timer 1
INT14_ISR, // CPU-Timer2
DATALOG_ISR, // Datalogging interrupt
RTOSINT_ISR, // RTOS interrupt
EMUINT_ISR, // Emulation interrupt
NMI_ISR, // Non-maskable interrupt
ILLEGAL_ISR, // Illegal operation TRAP
USER1_ISR, // User Defined trap 1
USER2_ISR, // User Defined trap 2
USER3_ISR, // User Defined trap 3
USER4_ISR, // User Defined trap 4
USER5_ISR, // User Defined trap 5
USER6_ISR, // User Defined trap 6
USER7_ISR, // User Defined trap 7
USER8_ISR, // User Defined trap 8
USER9_ISR, // User Defined trap 9
USER10_ISR, // User Defined trap 10
USER11_ISR, // User Defined trap 11
USER12_ISR, // User Defined trap 12
// Group 1 PIE Vectors
PDPINTA_ISR, // EV-A
PDPINTB_ISR, // EV-B
rsvd_ISR,
XINT1_ISR,
XINT2_ISR,
ADCINT_ISR, // ADC
TINT0_ISR, // Timer 0
WAKEINT_ISR, // WD
// Group 2 PIE Vectors
CMP1INT_ISR, // EV-A
CMP2INT_ISR, // EV-A
CMP3INT_ISR, // EV-A
T1PINT_ISR, // EV-A
T1CINT_ISR, // EV-A
T1UFINT_ISR, // EV-A
T1OFINT_ISR, // EV-A
rsvd_ISR,
// Group 3 PIE Vectors
T2PINT_ISR, // EV-A
T2CINT_ISR, // EV-A
T2UFINT_ISR, // EV-A
T2OFINT_ISR, // EV-A
CAPINT1_ISR, // EV-A
CAPINT2_ISR, // EV-A
CAPINT3_ISR, // EV-A
rsvd_ISR,
// Group 4 PIE Vectors
CMP4INT_ISR, // EV-B
CMP5INT_ISR, // EV-B
CMP6INT_ISR, // EV-B
T3PINT_ISR, // EV-B
T3CINT_ISR, // EV-B
T3UFINT_ISR, // EV-B
T3OFINT_ISR, // EV-B
rsvd_ISR,
// Group 5 PIE Vectors
T4PINT_ISR, // EV-B
T4CINT_ISR, // EV-B
T4UFINT_ISR, // EV-B
T4OFINT_ISR, // EV-B
CAPINT4_ISR, // EV-B
CAPINT5_ISR, // EV-B
CAPINT6_ISR, // EV-B
rsvd_ISR,
// Group 6 PIE Vectors
SPIRXINTA_ISR, // SPI-A
SPITXINTA_ISR, // SPI-A
rsvd_ISR,
rsvd_ISR,
MRINTA_ISR, // McBSP-A
MXINTA_ISR, // McBSP-A
rsvd_ISR,
rsvd_ISR,
// Group 7 PIE Vectors
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
// Group 8 PIE Vectors
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
// Group 9 PIE Vectors
SCIRXINTA_ISR, // SCI-A
SCITXINTA_ISR, // SCI-A
SCIRXINTB_ISR, // SCI-B
SCITXINTB_ISR, // SCI-B
ECAN0INTA_ISR, // eCAN
ECAN1INTA_ISR, // eCAN
rsvd_ISR,
rsvd_ISR,
// Group 10 PIE Vectors
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
// Group 11 PIE Vectors
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
// Group 12 PIE Vectors
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
};
void InitPieVectTable2(void)
{
int16 i;
Uint32 *Source = (void *) &PieVectTableInit;
Uint32 *Dest = (void *) PieVectTable;
EALLOW();
for(i=0; i < 128; i++)
*Dest++ = *Source++;
EDIS();
// Enable the PIE Vector Table
PieCtrlRegs->PIECRTL.bit.ENPIE = 1;
}
void xintf_timing(void)
{
// All Zones---------------------------------
// Timing for all zones based on XTIMCLK = SYSCLKOUT
XintfRegs->XINTCNF2.bit.XTIMCLK = 1;
// Buffer up to 3 writes
XintfRegs->XINTCNF2.bit.WRBUFF = 1;
// XCLKOUT is enabled
XintfRegs->XINTCNF2.bit.CLKOFF = 0;
// XCLKOUT = XTIMCLK
XintfRegs->XINTCNF2.bit.CLKMODE = 1;
// Zone 0------------------------------------
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
XintfRegs->XTIMING0.bit.XWRLEAD = 3;
XintfRegs->XTIMING0.bit.XWRACTIVE = 7;//1;
XintfRegs->XTIMING0.bit.XWRTRAIL = 3;
// Zone read timing
XintfRegs->XTIMING0.bit.XRDLEAD = 3;
XintfRegs->XTIMING0.bit.XRDACTIVE = 7;//2;
XintfRegs->XTIMING0.bit.XRDTRAIL = 3;//0;
// do not double all Zone read/write lead/active/trail timing
XintfRegs->XTIMING0.bit.X2TIMING = 1;//0
// Zone will not sample READY
XintfRegs->XTIMING0.bit.USEREADY = 0;
XintfRegs->XTIMING0.bit.READYMODE = 0;
// Size must be 1,1 - other values are reserved
XintfRegs->XTIMING0.bit.XSIZE = 3;
// Zone 2------------------------------------
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
XintfRegs->XTIMING2.bit.XWRLEAD = 1;
XintfRegs->XTIMING2.bit.XWRACTIVE = 1;//1;
XintfRegs->XTIMING2.bit.XWRTRAIL = 1;
// Zone read timing
XintfRegs->XTIMING2.bit.XRDLEAD = 1;
XintfRegs->XTIMING2.bit.XRDACTIVE = 2;//2;
XintfRegs->XTIMING2.bit.XRDTRAIL = 0;//0;
// do not double all Zone read/write lead/active/trail timing
XintfRegs->XTIMING2.bit.X2TIMING = 1;//0
// Zone will not sample READY
XintfRegs->XTIMING2.bit.USEREADY = 0;
XintfRegs->XTIMING2.bit.READYMODE = 0;
// Size must be 1,1 - other values are reserved
XintfRegs->XTIMING2.bit.XSIZE = 3;
// Zone 6------------------------------------
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
XintfRegs->XTIMING6.bit.XWRLEAD = 1;
XintfRegs->XTIMING6.bit.XWRACTIVE = 1;//1;
XintfRegs->XTIMING6.bit.XWRTRAIL = 1;
// Zone read timing
XintfRegs->XTIMING6.bit.XRDLEAD = 1;
XintfRegs->XTIMING6.bit.XRDACTIVE = 2;//2;
XintfRegs->XTIMING6.bit.XRDTRAIL = 0;//0;
// do not double all Zone read/write lead/active/trail timing
XintfRegs->XTIMING6.bit.X2TIMING = 0;//0
// Zone will not sample READY
XintfRegs->XTIMING6.bit.USEREADY = 0;
XintfRegs->XTIMING6.bit.READYMODE = 0;
// Size must be 1,1 - other values are reserved
XintfRegs->XTIMING6.bit.XSIZE = 3;
// Zone 7------------------------------------
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
XintfRegs->XTIMING7.bit.XWRLEAD = 1;
XintfRegs->XTIMING7.bit.XWRACTIVE = 1;
XintfRegs->XTIMING7.bit.XWRTRAIL = 1;
// Zone read timing
XintfRegs->XTIMING7.bit.XRDLEAD = 1;
XintfRegs->XTIMING7.bit.XRDACTIVE = 2;
XintfRegs->XTIMING7.bit.XRDTRAIL = 0;
// don't double all Zone read/write lead/active/trail timing
XintfRegs->XTIMING7.bit.X2TIMING = 0;
// Zone will not sample XREADY signal
XintfRegs->XTIMING7.bit.USEREADY = 0;
XintfRegs->XTIMING7.bit.READYMODE = 0;
// Size must be 1,1 - other values are reserved
XintfRegs->XTIMING7.bit.XSIZE = 3;
//Force a pipeline flush to ensure that the write to
//the last register configured occurs before returning.
asm(" RPT #7 || NOP");
}
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