📄 f2812_reg.h
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PINT rsvd7_2;
PINT rsvd7_3;
PINT rsvd7_4;
PINT rsvd7_5;
PINT rsvd7_6;
PINT rsvd7_7;
PINT rsvd7_8;
// Group 8 PIE Peripheral Vectors:
PINT rsvd8_1;
PINT rsvd8_2;
PINT rsvd8_3;
PINT rsvd8_4;
PINT rsvd8_5;
PINT rsvd8_6;
PINT rsvd8_7;
PINT rsvd8_8;
// Group 9 PIE Peripheral Vectors:
PINT RXAINT; // SCI-A
PINT TXAINT; // SCI-A
PINT RXBINT; // SCI-B
PINT TXBINT; // SCI-B
PINT ECAN0INTA; // eCAN
PINT ECAN1INTA; // eCAN
PINT rsvd9_7;
PINT rsvd9_8;
// Group 10 PIE Peripheral Vectors:
PINT rsvd10_1;
PINT rsvd10_2;
PINT rsvd10_3;
PINT rsvd10_4;
PINT rsvd10_5;
PINT rsvd10_6;
PINT rsvd10_7;
PINT rsvd10_8;
// Group 11 PIE Peripheral Vectors:
PINT rsvd11_1;
PINT rsvd11_2;
PINT rsvd11_3;
PINT rsvd11_4;
PINT rsvd11_5;
PINT rsvd11_6;
PINT rsvd11_7;
PINT rsvd11_8;
// Group 12 PIE Peripheral Vectors:
PINT rsvd12_1;
PINT rsvd12_2;
PINT rsvd12_3;
PINT rsvd12_4;
PINT rsvd12_5;
PINT rsvd12_6;
PINT rsvd12_7;
PINT rsvd12_8;
};
//__________________________________________________________________________________________________
// XINTF timing register bit definitions:
struct XTIMING_BITS { // bits description
Uint16 XWRTRAIL:2; // 1:0 Write access trail timing
Uint16 XWRACTIVE:3; // 4:2 Write access active timing
Uint16 XWRLEAD:2; // 6:5 Write access lead timing
Uint16 XRDTRAIL:2; // 8:7 Read access trail timing
Uint16 XRDACTIVE:3; // 11:9 Read access active timing
Uint16 XRDLEAD:2; // 13:12 Read access lead timing
Uint16 USEREADY:1; // 14 Extend access using HW waitstates
Uint16 READYMODE:1; // 15 Ready mode
Uint16 XSIZE:2; // 17:16 XINTF bus width - must be written as 11b
Uint16 rsvd1:4; // 21:18 reserved
Uint16 X2TIMING:1; // 22 Double lead/active/trail timing
Uint16 rsvd3:9; // 31:23 reserved
};
union XTIMING_REG {
Uint32 all;
struct XTIMING_BITS bit;
};
// XINTF control register bit definitions:
struct XINTCNF2_BITS { // bits description
Uint16 WRBUFF:2; // 1:0 Write buffer depth
Uint16 CLKMODE:1; // 2 Ratio for XCLKOUT with respect to XTIMCLK
Uint16 CLKOFF:1; // 3 Disable XCLKOUT
Uint16 rsvd1:2; // 5:4 reserved
Uint16 WLEVEL:2; // 7:6 Current level of the write buffer
Uint16 MPNMC:1; // 8 Micro-processor/micro-computer mode
Uint16 HOLD:1; // 9 Hold enable/disable
Uint16 HOLDS:1; // 10 Current state of HOLDn input
Uint16 HOLDAS:1; // 11 Current state of HOLDAn output
Uint16 rsvd2:4; // 15:12 reserved
Uint16 XTIMCLK:3; // 18:16 Ratio for XTIMCLK
Uint16 rsvd3:13; // 31:19 reserved
};
union XINTCNF2_REG {
Uint32 all;
struct XINTCNF2_BITS bit;
};
// XINTF bank switching register bit definitions:
struct XBANK_BITS { // bits description
Uint16 BANK:3; // 2:0 Zone for which banking is enabled
Uint16 BCYC:3; // 5:3 XTIMCLK cycles to add
Uint16 rsvd:10; // 15:6 reserved
};
union XBANK_REG {
Uint16 all;
struct XBANK_BITS bit;
};
//---------------------------------------------------------------------------
// XINTF Register File:
//
struct XINTF_REGS {
union XTIMING_REG XTIMING0;
union XTIMING_REG XTIMING1;
union XTIMING_REG XTIMING2;
Uint32 rsvd1[3];
union XTIMING_REG XTIMING6;
union XTIMING_REG XTIMING7;
Uint32 rsvd2[2];
union XINTCNF2_REG XINTCNF2;
Uint32 rsvd3;
union XBANK_REG XBANK;
Uint16 rsvd4;
Uint16 XREVISION;
Uint16 rsvd5[5];
};
//_____________________________________________________________________________________________________
//----------------------------------------------------
// GPIO A mux control register bit definitions */
//
//
struct GPAMUX_BITS { // bits description
Uint16 PWM1_GPIOA0:1; // 0
Uint16 PWM2_GPIOA1:1; // 1
Uint16 PWM3_GPIOA2:1; // 2
Uint16 PWM4_GPIOA3:1; // 3
Uint16 PWM5_GPIOA4:1; // 4
Uint16 PWM6_GPIOA5:1; // 5
Uint16 T1PWM_GPIOA6:1; // 6
Uint16 T2PWM_GPIOA7:1; // 7
Uint16 CAP1Q1_GPIOA8:1; // 8
Uint16 CAP2Q2_GPIOA9:1; // 9
Uint16 CAP3QI1_GPIOA10:1; // 10
Uint16 TDIRA_GPIOA11:1; // 11
Uint16 TCLKINA_GPIOA12:1; // 12
Uint16 C1TRIP_GPIOA13:1; // 13
Uint16 C2TRIP_GPIOA14:1; // 14
Uint16 C3TRIP_GPIOA15:1; // 15
};
union GPAMUX_REG {
Uint16 all;
struct GPAMUX_BITS bit;
};
//---------------------------------------------------------------------------------------
// GPIO A Direction control register bit definitions
//
//
struct GPADIR_BITS { // bits description
Uint16 GPIOA0:1; // 0
Uint16 GPIOA1:1; // 1
Uint16 GPIOA2:1; // 2
Uint16 GPIOA3:1; // 3
Uint16 GPIOA4:1; // 4
Uint16 GPIOA5:1; // 5
Uint16 GPIOA6:1; // 6
Uint16 GPIOA7:1; // 7
Uint16 GPIOA8:1; // 8
Uint16 GPIOA9:1; // 9
Uint16 GPIOA10:1; // 10
Uint16 GPIOA11:1; // 11
Uint16 GPIOA12:1; // 12
Uint16 GPIOA13:1; // 13
Uint16 GPIOA14:1; // 14
Uint16 GPIOA15:1; // 15
};
union GPADIR_REG {
Uint16 all;
struct GPADIR_BITS bit;
};
//----------------------------------
// GPA Qualregister bit definitions
//
//
struct GPAQUAL_BITS { // bits description
Uint16 QUALPRD:8; // 0:7 Qualification Sampling Period
Uint16 rsvd1:8; // 15:8 reserved
};
union GPAQUAL_REG {
Uint16 all;
struct GPAQUAL_BITS bit;
};
//---------------------------------------------------------------------------------------
// GPIO A Data register bit definitions
//
//
struct GPADAT_BITS { // bits description
Uint16 GPIOA0:1; // 0
Uint16 GPIOA1:1; // 1
Uint16 GPIOA2:1; // 2
Uint16 GPIOA3:1; // 3
Uint16 GPIOA4:1; // 4
Uint16 GPIOA5:1; // 5
Uint16 GPIOA6:1; // 6
Uint16 GPIOA7:1; // 7
Uint16 GPIOA8:1; // 8
Uint16 GPIOA9:1; // 9
Uint16 GPIOA10:1; // 10
Uint16 GPIOA11:1; // 11
Uint16 GPIOA12:1; // 12
Uint16 GPIOA13:1; // 13
Uint16 GPIOA14:1; // 14
Uint16 GPIOA15:1; // 15
};
union GPADAT_REG {
Uint16 all;
struct GPADAT_BITS bit;
};
//---------------------------------------------------------------------------------------
// GPIO A Data set bit definitions
//
//
struct GPASET_BITS { // bits description
Uint16 GPIOA0:1; // 0
Uint16 GPIOA1:1; // 1
Uint16 GPIOA2:1; // 2
Uint16 GPIOA3:1; // 3
Uint16 GPIOA4:1; // 4
Uint16 GPIOA5:1; // 5
Uint16 GPIOA6:1; // 6
Uint16 GPIOA7:1; // 7
Uint16 GPIOA8:1; // 8
Uint16 GPIOA9:1; // 9
Uint16 GPIOA10:1; // 10
Uint16 GPIOA11:1; // 11
Uint16 GPIOA12:1; // 12
Uint16 GPIOA13:1; // 13
Uint16 GPIOA14:1; // 14
Uint16 GPIOA15:1; // 15
};
union GPASET_REG {
Uint16 all;
struct GPASET_BITS bit;
};
//---------------------------------------------------------------------------------------
// GPIO A Data clear register bit definitions
//
//
struct GPACLEAR_BITS { // bits description
Uint16 GPIOA0:1; // 0
Uint16 GPIOA1:1; // 1
Uint16 GPIOA2:1; // 2
Uint16 GPIOA3:1; // 3
Uint16 GPIOA4:1; // 4
Uint16 GPIOA5:1; // 5
Uint16 GPIOA6:1; // 6
Uint16 GPIOA7:1; // 7
Uint16 GPIOA8:1; // 8
Uint16 GPIOA9:1; // 9
Uint16 GPIOA10:1; // 10
Uint16 GPIOA11:1; // 11
Uint16 GPIOA12:1; // 12
Uint16 GPIOA13:1; // 13
Uint16 GPIOA14:1; // 14
Uint16 GPIOA15:1; // 15
};
union GPACLEAR_REG {
Uint16 all;
struct GPACLEAR_BITS bit;
};
//---------------------------------------------------------------------------------------
// GPIO A Data toggle register bit definitions
//
//
struct GPATOGGLE_BITS { // bits description
Uint16 GPIOA0:1; // 0
Uint16 GPIOA1:1; // 1
Uint16 GPIOA2:1; // 2
Uint16 GPIOA3:1; // 3
Uint16 GPIOA4:1; // 4
Uint16 GPIOA5:1; // 5
Uint16 GPIOA6:1; // 6
Uint16 GPIOA7:1; // 7
Uint16 GPIOA8:1; // 8
Uint16 GPIOA9:1; // 9
Uint16 GPIOA10:1; // 10
Uint16 GPIOA11:1; // 11
Uint16 GPIOA12:1; // 12
Uint16 GPIOA13:1; // 13
Uint16 GPIOA14:1; // 14
Uint16 GPIOA15:1; // 15
};
union GPATOGGLE_REG {
Uint16 all;
struct GPATOGGLE_BITS bit;
};
//---------------------------------------------------------------------------------
// GPIO B mux control register bit definitions
//
//
struct GPBMUX_BITS { // bits description
Uint16 PWM7_GPIOB0:1; // 0
Uint16 PWM8_GPIOB1:1; // 1
Uint16 PWM9_GPIOB2:1; // 2
Uint16 PWM10_GPIOB3:1; // 3
Uint16 PWM11_GPIOB4:1; // 4
Uint16 PWM12_GPIOB5:1; // 5
Uint16 T3PWM_GPIOB6:1; // 6
Uint16 T4PWM_GPIOB7:1; // 7
Uint16 CAP4Q1_GPIOB8:1; // 8
Uint16 CAP5Q2_GPIOB9:1; // 9
Uint16 CAP6QI2_GPIOB10:1; // 10
Uint16 TDIRB_GPIOB11:1; // 11
Uint16 TCLKINB_GPIOB12:1; // 12
Uint16 C4TRIP_GPIOB13:1; // 13
Uint16 C5TRIP_GPIOB14:1; // 14
Uint16 C6TRIP_GPIOB15:1; // 15
};
union GPBMUX_REG {
Uint16 all;
struct GPBMUX_BITS bit;
};
//---------------------------------------------------------------------------------------
// GPIO B Direction control register bit definitions
//
//
struct GPBDIR_BITS { // bits description
Uint16 GPIOB0:1; // 0
Uint16 GPIOB1:1; // 1
Uint16 GPIOB2:1; // 2
Uint16 GPIOB3:1; // 3
Uint16 GPIOB4:1; // 4
Uint16 GPIOB5:1; // 5
Uint16 GPIOB6:1; // 6
Uint16 GPIOB7:1; // 7
Uint16 GPIOB8:1; // 8
Uint16 GPIOB9:1; // 9
Uint16 GPIOB10:1; // 10
Uint16 GPIOB11:1; // 11
Uint16 GPIOB12:1; // 12
Uint16 GPIOB13:1; // 13
Uint16 GPIOB14:1; // 14
Uint16 GPIOB15:1; // 15
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