📄 f2812_reg.h
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#ifndef __F2812_REG_H__
#define __F2812_REG_H__
#ifdef __cplusplus
extern "C" {
#endif
extern cregister volatile unsigned int IFR;
extern cregister volatile unsigned int IER;
#define EINT() asm(" clrc INTM")
#define DINT() asm(" setc INTM")
#define ERTM() asm(" clrc DBGM")
#define DRTM() asm(" setc DBGM")
#define EALLOW() asm(" EALLOW")
#define EDIS() asm(" EDIS")
#define ESTOP0() asm(" ESTOP0")
#define M_INT1 0x0001
#define M_INT2 0x0002
#define M_INT3 0x0004
#define M_INT4 0x0008
#define M_INT5 0x0010
#define M_INT6 0x0020
#define M_INT7 0x0040
#define M_INT8 0x0080
#define M_INT9 0x0100
#define M_INT10 0x0200
#define M_INT11 0x0400
#define M_INT12 0x0800
#define M_INT13 0x1000
#define M_INT14 0x2000
#define M_DLOG 0x4000
#define M_RTOS 0x8000
#define BIT0 0x0001
#define BIT1 0x0002
#define BIT2 0x0004
#define BIT3 0x0008
#define BIT4 0x0010
#define BIT5 0x0020
#define BIT6 0x0040
#define BIT7 0x0080
#define BIT8 0x0100
#define BIT9 0x0200
#define BIT10 0x0400
#define BIT11 0x0800
#define BIT12 0x1000
#define BIT13 0x2000
#define BIT14 0x4000
#define BIT15 0x8000
//---------------------------------------------------------------------------
// System Control Individual Register Bit Definitions:
//
// High speed peripheral clock register bit definitions:
struct HISPCP_BITS { // bits description
Uint16 HSPCLK:3; // 2:0 Rate relative to SYSCLKOUT
Uint16 rsvd1:13; // 15:3 reserved
};
union HISPCP_REG {
Uint16 all;
struct HISPCP_BITS bit;
};
// Low speed peripheral clock register bit definitions:
struct LOSPCP_BITS { // bits description
Uint16 LSPCLK:3; // 2:0 Rate relative to SYSCLKOUT
Uint16 rsvd1:13; // 15:3 reserved
};
union LOSPCP_REG {
Uint16 all;
struct LOSPCP_BITS bit;
};
// Peripheral clock control register bit definitions:
struct PCLKCR_BITS { // bits description
Uint16 EVAENCLK:1; // 0 Enable high speed clk to EV-A
Uint16 EVBENCLK:1; // 1 Enable high speed clk to EV-B
Uint16 rsvd1:1; // 2
Uint16 ADCENCLK:1; // 3 Enable high speed clk to ADC
Uint16 rsvd2:4; // 7:4 reserved
Uint16 SPIENCLK:1; // 8 Enable low speed clk to SPI
Uint16 rsvd3:1; // 9 reserved
Uint16 SCIAENCLK:1; // 10 Enable low speed clk to SCI-A
Uint16 SCIBENCLK:1; // 11 Enable low speed clk to SCI-B
Uint16 MCBSPENCLK:1; // 12 Enable low speed clk to McBSP
Uint16 rsvd4:1; // 13 reserved
Uint16 ECANENCLK:1; // 14 Enable system clk to eCAN
};
union PCLKCR_REG {
Uint16 all;
struct PCLKCR_BITS bit;
};
// PLL control register bit definitions:
struct PLLCR_BITS { // bits description
Uint16 DIV:4; // 3:0 Set clock ratio for the PLL
Uint16 rsvd1:12; // 15:4 reserved
};
union PLLCR_REG {
Uint16 all;
struct PLLCR_BITS bit;
};
// Low Power Mode 0 control register bit definitions:
struct LPMCR0_BITS { // bits description
Uint16 LPM:2; // 1:0 Set the low power mode
Uint16 QUALSTDBY:6; // 7:2 Qualification
Uint16 rsvd1:8; // 15:8 reserved
};
union LPMCR0_REG {
Uint16 all;
struct LPMCR0_BITS bit;
};
// Low Power Mode 1 control register bit definitions:
struct LPMCR1_BITS { // bits description
Uint16 XINT1:1; // 0 Enable XINT1 to wake the device from standby
Uint16 XNMI:1; // 1 Enable XMNI to wake the device from standby
Uint16 WDINT:1; // 2 Enable watchdog interrupt to wake the device from standby
Uint16 T1CTRIP:1; // 3 Enable T1CTRIP to wake the device from standby
Uint16 T2CTRIP:1; // 4 Enable T2CTRIP to wake the device from standby
Uint16 T3CTRIP:1; // 5 Enable T3CTRIP to wake the device from standby
Uint16 T4CTRIP:1; // 6 Enable T4CTRIP to wake the device from standby
Uint16 C1TRIP:1; // 7 Enable C1TRIP to wake the device from standby
Uint16 C2TRIP:1; // 8 Enable C2TRIP to wake the device from standby
Uint16 C3TRIP:1; // 9 Enable C3TRIP to wake the device from standby
Uint16 C4TRIP:1; // 10 Enable C4TRIP to wake the device from standby
Uint16 C5TRIP:1; // 11 Enable C5TRIP to wake the device from standby
Uint16 C6TRIP:1; // 12 Enable C6TRIP to wake the device from standby
Uint16 SCIRXA:1; // 13 Enable SCIRXA to wake the device from standby
Uint16 SCIRXB:1; // 14 Enable SCIRXB to wake the device from standby
Uint16 CANRX:1; // 15 Enable CANRX to wake the device from standby
};
union LPMCR1_REG {
Uint16 all;
struct LPMCR1_BITS bit;
};
struct SYS_CTRL_REGS {
Uint16 rsvd1[10]; // 0-9
union HISPCP_REG HISPCP; // 10: High-speed peripheral clock pre-scaler
union LOSPCP_REG LOSPCP; // 11: Low-speed peripheral clock pre-scaler
union PCLKCR_REG PCLKCR; // 12: Peripheral clock control register
Uint16 rsvd2; // 13: reserved
union LPMCR0_REG LPMCR0; // 14: Low-power mode control register 0
union LPMCR1_REG LPMCR1; // 15: Low-power mode control register 1
Uint16 rsvd3; // 16: reserved
union PLLCR_REG PLLCR; // 17: PLL control register
// No bit definitions are defined for SCSR because
// a read-modify-write instruction can clear the WDOVERRIDE bit
Uint16 SCSR; // 18: System control and status register
Uint16 WDCNTR; // 19: WD counter register
Uint16 rsvd4; // 20
Uint16 WDKEY; // 21: WD reset key register
Uint16 rsvd5[3]; // 22-24
// No bit definitions are defined for WDCR because
// the proper value must be written to the WDCHK field
// whenever writing to this register.
Uint16 WDCR; // 25: WD timer control register
Uint16 rsvd6[6]; // 26-31
};
//____________________________________________________________________________________________________________
//---------------------------------------------------------------------------
// PIE Control Register Bit Definitions:
//
// PIECTRL: Register bit definitions:
struct PIECTRL_BITS { // bits description
Uint16 ENPIE:1; // 0 Enable PIE block
Uint16 PIEVECT:15; // 15:1 Fetched vector address
};
union PIECTRL_REG {
Uint16 all;
struct PIECTRL_BITS bit;
};
// PIEIER: Register bit definitions:
struct PIEIER_BITS { // bits description
Uint16 INTx1:1; // 0 INTx.1
Uint16 INTx2:1; // 1 INTx.2
Uint16 INTx3:1; // 2 INTx.3
Uint16 INTx4:1; // 3 INTx.4
Uint16 INTx5:1; // 4 INTx.5
Uint16 INTx6:1; // 5 INTx.6
Uint16 INTx7:1; // 6 INTx.7
Uint16 INTx8:1; // 7 INTx.8
Uint16 rsvd:8; // 15:8 reserved
};
union PIEIER_REG {
Uint16 all;
struct PIEIER_BITS bit;
};
// PIEIFR: Register bit definitions:
struct PIEIFR_BITS { // bits description
Uint16 INTx1:1; // 0 INTx.1
Uint16 INTx2:1; // 1 INTx.2
Uint16 INTx3:1; // 2 INTx.3
Uint16 INTx4:1; // 3 INTx.4
Uint16 INTx5:1; // 4 INTx.5
Uint16 INTx6:1; // 5 INTx.6
Uint16 INTx7:1; // 6 INTx.7
Uint16 INTx8:1; // 7 INTx.8
Uint16 rsvd:8; // 15:8 reserved
};
union PIEIFR_REG {
Uint16 all;
struct PIEIFR_BITS bit;
};
// PIEACK: Register bit definitions:
struct PIEACK_BITS { // bits description
Uint16 ACK1:1; // 0 Acknowledge PIE interrupt group 1
Uint16 ACK2:1; // 1 Acknowledge PIE interrupt group 2
Uint16 ACK3:1; // 2 Acknowledge PIE interrupt group 3
Uint16 ACK4:1; // 3 Acknowledge PIE interrupt group 4
Uint16 ACK5:1; // 4 Acknowledge PIE interrupt group 5
Uint16 ACK6:1; // 5 Acknowledge PIE interrupt group 6
Uint16 ACK7:1; // 6 Acknowledge PIE interrupt group 7
Uint16 ACK8:1; // 7 Acknowledge PIE interrupt group 8
Uint16 ACK9:1; // 8 Acknowledge PIE interrupt group 9
Uint16 ACK10:1; // 9 Acknowledge PIE interrupt group 10
Uint16 ACK11:1; // 10 Acknowledge PIE interrupt group 11
Uint16 ACK12:1; // 11 Acknowledge PIE interrupt group 12
Uint16 rsvd:4; // 15:12 reserved
};
union PIEACK_REG {
Uint16 all;
struct PIEACK_BITS bit;
};
//---------------------------------------------------------------------------
// PIE Control Register File:
//
struct PIE_CTRL_REGS {
union PIECTRL_REG PIECRTL; // PIE control register
union PIEACK_REG PIEACK; // PIE acknowledge
union PIEIER_REG PIEIER1; // PIE INT1 IER register
union PIEIFR_REG PIEIFR1; // PIE INT1 IFR register
union PIEIER_REG PIEIER2; // PIE INT2 IER register
union PIEIFR_REG PIEIFR2; // PIE INT2 IFR register
union PIEIER_REG PIEIER3; // PIE INT3 IER register
union PIEIFR_REG PIEIFR3; // PIE INT3 IFR register
union PIEIER_REG PIEIER4; // PIE INT4 IER register
union PIEIFR_REG PIEIFR4; // PIE INT4 IFR register
union PIEIER_REG PIEIER5; // PIE INT5 IER register
union PIEIFR_REG PIEIFR5; // PIE INT5 IFR register
union PIEIER_REG PIEIER6; // PIE INT6 IER register
union PIEIFR_REG PIEIFR6; // PIE INT6 IFR register
union PIEIER_REG PIEIER7; // PIE INT7 IER register
union PIEIFR_REG PIEIFR7; // PIE INT7 IFR register
union PIEIER_REG PIEIER8; // PIE INT8 IER register
union PIEIFR_REG PIEIFR8; // PIE INT8 IFR register
union PIEIER_REG PIEIER9; // PIE INT9 IER register
union PIEIFR_REG PIEIFR9; // PIE INT9 IFR register
union PIEIER_REG PIEIER10; // PIE INT10 IER register
union PIEIFR_REG PIEIFR10; // PIE INT10 IFR register
union PIEIER_REG PIEIER11; // PIE INT11 IER register
union PIEIFR_REG PIEIFR11; // PIE INT11 IFR register
union PIEIER_REG PIEIER12; // PIE INT12 IER register
union PIEIFR_REG PIEIFR12; // PIE INT12 IFR register
};
//________________________________________________________________________________________________________
struct PIE_VECT_TABLE {
// Reset is never fetched from this table.
// It will always be fetched from 0x3FFFC0 in either
// boot ROM or XINTF Zone 7 depending on the state of
// the XMP/MC input signal. On the F2810 it is always
// fetched from boot ROM.
PINT PIE1_RESERVED;
PINT PIE2_RESERVED;
PINT PIE3_RESERVED;
PINT PIE4_RESERVED;
PINT PIE5_RESERVED;
PINT PIE6_RESERVED;
PINT PIE7_RESERVED;
PINT PIE8_RESERVED;
PINT PIE9_RESERVED;
PINT PIE10_RESERVED;
PINT PIE11_RESERVED;
PINT PIE12_RESERVED;
PINT PIE13_RESERVED;
// Non-Peripheral Interrupts:
PINT XINT13; // XINT13
PINT TINT2; // CPU-Timer2
PINT DATALOG; // Datalogging interrupt
PINT RTOSINT; // RTOS interrupt
PINT EMUINT; // Emulation interrupt
PINT XNMI; // Non-maskable interrupt
PINT ILLEGAL; // Illegal operation TRAP
PINT USER1; // User Defined trap 1
PINT USER2; // User Defined trap 2
PINT USER3; // User Defined trap 3
PINT USER4; // User Defined trap 4
PINT USER5; // User Defined trap 5
PINT USER6; // User Defined trap 6
PINT USER7; // User Defined trap 7
PINT USER8; // User Defined trap 8
PINT USER9; // User Defined trap 9
PINT USER10; // User Defined trap 10
PINT USER11; // User Defined trap 11
PINT USER12; // User Defined trap 12
// Group 1 PIE Peripheral Vectors:
PINT PDPINTA; // EV-A
PINT PDPINTB; // EV-B
PINT rsvd1_3;
PINT XINT1;
PINT XINT2;
PINT ADCINT; // ADC
PINT TINT0; // Timer 0
PINT WAKEINT; // WD
// Group 2 PIE Peripheral Vectors:
PINT CMP1INT; // EV-A
PINT CMP2INT; // EV-A
PINT CMP3INT; // EV-A
PINT T1PINT; // EV-A
PINT T1CINT; // EV-A
PINT T1UFINT; // EV-A
PINT T1OFINT; // EV-A
PINT rsvd2_8;
// Group 3 PIE Peripheral Vectors:
PINT T2PINT; // EV-A
PINT T2CINT; // EV-A
PINT T2UFINT; // EV-A
PINT T2OFINT; // EV-A
PINT CAPINT1; // EV-A
PINT CAPINT2; // EV-A
PINT CAPINT3; // EV-A
PINT rsvd3_8;
// Group 4 PIE Peripheral Vectors:
PINT CMP4INT; // EV-B
PINT CMP5INT; // EV-B
PINT CMP6INT; // EV-B
PINT T3PINT; // EV-B
PINT T3CINT; // EV-B
PINT T3UFINT; // EV-B
PINT T3OFINT; // EV-B
PINT rsvd4_8;
// Group 5 PIE Peripheral Vectors:
PINT T4PINT; // EV-B
PINT T4CINT; // EV-B
PINT T4UFINT; // EV-B
PINT T4OFINT; // EV-B
PINT CAPINT4; // EV-B
PINT CAPINT5; // EV-B
PINT CAPINT6; // EV-B
PINT rsvd5_8;
// Group 6 PIE Peripheral Vectors:
PINT SPIRXINTA; // SPI-A
PINT SPITXINTA; // SPI-A
PINT rsvd6_3;
PINT rsvd6_4;
PINT MRINTA; // McBSP-A
PINT MXINTA; // McBSP-A
PINT rsvd6_7;
PINT rsvd6_8;
// Group 7 PIE Peripheral Vectors:
PINT rsvd7_1;
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