📄 designer.log
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Actel Designer Software
Version: 8.0.3.7
Release: v8.0 SP2
Warning: The file you want to import is not part of the Libero project; do you want to copy it
into your current project folder? [YES]
Netlist Reading Time = 1.0 seconds
Imported the files:
D:\LCD_1602\synthesis\LCD_Top.edn
D:\LCD_1602\synthesis\LCD_Top_sdc.sdc
D:\LCD_1602\constraint\LCD_Top.pdc
The Import command succeeded ( 00:00:07 )
The design D:\LCD_1602\designer\impl1\LCD_Top.adb was last modified by software version
8.0.1.13.
Opened an existing Libero design D:\LCD_1602\designer\impl1\LCD_Top.adb.
'BA_NAME' set to 'LCD_Top_ba'
The Execute Script command succeeded ( 00:00:00 )
=====================================================================
Parameters used to run compile:
===============================
Family : Fusion
Device : AFS600
Package : 256 FBGA
Source : D:\LCD_1602\synthesis\LCD_Top.edn
D:\LCD_1602\synthesis\LCD_Top_sdc.sdc
D:\LCD_1602\constraint\LCD_Top.pdc
Format : EDIF
Topcell : LCD_Top
Speed grade : -2
Temp : 0:25:70
Voltage : 1.58:1.50:1.42
=====================================================================
Compile starts ...
Warning: CMP201: Net: U1/U1/Core_GLB is floating
Warning: CMP201: Net: U1/U1/Core_GLC is floating
Warning: CMP201: Net: U1/U1/Core_LOCK is floating
Warning: CMP201: Net: U1/U1/Core_YB is floating
Warning: CMP201: Net: U1/U1/Core_YC is floating
Netlist Optimization Report
===========================
Optimized macros:
- Dangling net drivers: 0
- Buffers: 1
- Inverters: 1
- Tieoff: 0
- Logic combining: 10
Total macros optimized 12
Warning: CMP503: Remapped 10 enable flip-flop(s) to a 2-tile implementation because the CLR/PRE
pin on the enable flip-flop is not being driven by a global net.
There were 0 error(s) and 6 warning(s) in this design.
=====================================================================
Reading previous post-compile physical placement constraints.
There were 0 error(s) and 0 warning(s).
=====================================================================
Reading user pdc (Physical Design Constraints) file(s) postcompile
There were 0 error(s) and 0 warning(s) in reading the user pdc.
=====================================================================
Compile report:
===============
CORE Used: 486 Total: 13824 (3.52%)
IO (W/ clocks) Used: 13 Total: 119 (10.92%)
Differential IO Used: 0 Total: 58 (0.00%)
GLOBAL (Chip+Quadrant) Used: 6 Total: 18 (33.33%)
PLL Used: 1 Total: 2 (50.00%)
RAM/FIFO Used: 0 Total: 24 (0.00%)
Low Static ICC Used: 0 Total: 1 (0.00%)
FlashROM Used: 0 Total: 1 (0.00%)
User JTAG Used: 0 Total: 1 (0.00%)
RC oscillator Used: 0 Total: 1 (0.00%)
XTL oscillator Used: 0 Total: 1 (0.00%)
NVM Used: 0 Total: 2 (0.00%)
AB Used: 0 Total: 1 (0.00%)
AnalogIO Used: 0 Total: 46 (0.00%)
VRPSM Used: 0 Total: 1 (0.00%)
No-Glitch MUX Used: 0 Total: 2 (0.00%)
Global Information:
Type | Used | Total
----------------|--------|-------------
Chip global | 6 | 6 (100.00%)
Quadrant global | 0 | 12 (0.00%)
Core Information:
Type | Instances | Core tiles
--------|--------------|-----------
COMB | 251 | 251
SEQ | 225 | 235
I/O Function:
Type | w/o register | w/ register | w/ DDR register
------------------------------|---------------|--------------|----------------
Input I/O | 2 | 0 | 0
Output I/O | 11 | 0 | 0
Bidirectional I/O | 0 | 0 | 0
Differential Input I/O Pairs | 0 | 0 | 0
Differential Output I/O Pairs | 0 | 0 | 0
I/O Technology:
| Voltages | I/Os
--------------------------------|-------|-------|-------|--------|--------------
I/O Standard(s) | Vcci | Vref | Input | Output | Bidirectional
--------------------------------|-------|-------|-------|--------|--------------
LVTTL | 3.30v | N/A | 2 | 11 | 0
Net information report:
=======================
The following nets drive enable flip-flops that have been remapped to a 2-tile implementation:
EffCnt Type Name
--------------------------
9 SET/RESET_NET Net : rst_c_1
Driver: rst_pad_1
1 SET/RESET_NET Net : rst_c_0
Driver: rst_pad_0
The following nets have been assigned to a chip global resource:
Fanout Type Name
--------------------------
216 CLK_NET Net : clk_LCD
Driver: U1/clk_BUF_inferred_clock/U_CLKSRC
Source: NETLIST
98 INT_NET Net : I_1
Driver: I_1/U_CLKSRC
Source: NETLIST
97 INT_NET Net : U2.state[4]
Driver: I_2/U_CLKSRC
Source: NETLIST
93 INT_NET Net : U2.state[5]
Driver: I_3/U_CLKSRC
Source: NETLIST
93 INT_NET Net : I_4
Driver: I_4/U_CLKSRC
Source: NETLIST
11 CLK_NET Net : U1/clk_counter
Driver: U1/U1/Core
Source: ESSENTIAL
High fanout nets in the post compile netlist:
Fanout Type Name
--------------------------
12 SET/RESET_NET Net : rst_c_0
Driver: rst_pad_0
12 SET/RESET_NET Net : rst_c_1
Driver: rst_pad_1
10 INT_NET Net : U2/N_587
Driver: U2/state_ns_o2_i_a2[6]
9 INT_NET Net : U2/state_ns[7]
Driver: U2/state_ns_o2_0[7]
9 INT_NET Net : U2/disp_count_9_i_o2[0]
Driver: U2/disp_count_9_i_o2[0]
8 SET/RESET_NET Net : rst_c
Driver: rst_pad
8 INT_NET Net : U1/clk_BUF6
Driver: U1/clk_BUF6
7 INT_NET Net : rst_c_0_0
Driver: rst_pad_0_0
7 INT_NET Net : U2/state_0[6]
Driver: U2/state_0[6]
7 INT_NET Net : U2/N_513
Driver: U2/DB8_13_1_o2[0]
Nets that are candidates for clock assignment and the resulting fanout:
Fanout Type Name
--------------------------
36 SET/RESET_NET Net : rst_c
Driver: rst_pad
10 INT_NET Net : U2/N_587
Driver: U2/state_ns_o2_i_a2[6]
9 INT_NET Net : U2/state_ns[7]
Driver: U2/state_ns_o2_0[7]
9 INT_NET Net : U2/disp_count_9_i_o2[0]
Driver: U2/disp_count_9_i_o2[0]
8 INT_NET Net : U1/clk_BUF6
Driver: U1/clk_BUF6
7 INT_NET Net : U2/state_0[6]
Driver: U2/state_0[6]
7 INT_NET Net : U2/N_513
Driver: U2/DB8_13_1_o2[0]
6 INT_NET Net : U2/state[6]
Driver: U2/state[6]
6 INT_NET Net : U1/count[3]
Driver: U1/count[3]
6 INT_NET Net : U1/DWACT_FINC_E[0]
Driver: U1/un6_count_1_I_16
SDC Import: Starting final constraints validation...
The Compile command succeeded ( 00:00:05 )
I/O Bank Assigner detected (1) out of (5) I/O Bank(s) with locked I/O technologies.
Running I/O Bank Assigner.
I/O Bank Assigner completed successfully.
Planning global net placement...
Global net placement completed successfully.
o - o - o - o - o - o
Placer Started: Mon Oct 15 14:11:22 2007
Placer Finished: Mon Oct 15 14:11:27 2007
Total Placer CPU Time: 00:00:05
o - o - o - o - o - o
Timing-driven Router
Design: LCD_Top Started: Mon Oct 15 14:11:31 2007
Iterative improvement...
Timing-driven Router completed successfully.
Design: LCD_Top
Finished: Mon Oct 15 14:11:51 2007
Total CPU Time: 00:00:20 Total Elapsed Time: 00:00:20
o - o - o - o - o - o
Loading the Timing data for the design.
Finished loading the Timing data.
TIMER: Max delay timing requirements have been met.
The Layout command succeeded ( 00:00:38 )
Back-annotated to the file(s):
.\LCD_Top_ba.sdf
The Back-Annotate command succeeded ( 00:00:01 )
Warning: File D:\LCD_1602\designer\impl1\LCD_Top.pdb
already exists.
Do you want to replace the file? [YES]
The Export-map command succeeded ( 00:00:21 )
Warning: Overwriting the existing file: D:\LCD_1602\designer\impl1\LCD_Top.pdb.
Warning: A lock has been established on this design.
This lock may be due from a previous aborted session or
the design may currently be in use by another session.
Locked by: shoujinqiao
Hostname: SHOUJINQIAO
ExecutableID: C:\Libero\FlashPro\bin\FlashPro.exe.
Would you like to recover the unsaved edits during the opening of the design? [YES]
Wrote to the file: D:\LCD_1602\designer\impl1\LCD_Top.pdb
The Generate programming file command succeeded ( 00:01:12 )
Design saved to file D:\LCD_1602\designer\impl1\LCD_Top.adb.
Design closed.
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