lcd_top_ba.sdf

lcd 1602 xianshi kongzhiqudong

(DELAYFILE
 (SDFVERSION "2.1")
 (DESIGN "LCD_Top")
 (DATE "Mon Oct 15 14:14:58 2007")
 (VENDOR "ACTEL")
 (PROGRAM "Actel Designer Software, Release v8.0 SP2 Copyright (C) 1989-2007 Actel Corp. ")
 (VERSION "8.0.3.7")
 (DIVIDER /)
 (VOLTAGE 1.58:1.50:1.43)
 (PROCESS "best:nom:worst")
 (TEMPERATURE 0:25:70)
 (TIMESCALE 100ps)

 (CELL
 (CELLTYPE "NOR2B")
 (INSTANCE U2\/LCD_EN_i)
 (DELAY
  (ABSOLUTE
     (PORT A (4.32:5.25:5.73) (4.41:5.35:5.84))
     (IOPATH A Y (2.63:3.23:3.65) (2.77:3.40:3.84))
     (PORT B (11.20:13.58:14.83) (10.72:13.00:14.19))
     (IOPATH B Y (3.18:3.91:4.41) (3.40:4.17:4.71))
  )
 )
 )
 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_First_Buf\[73\])
 (DELAY
  (ABSOLUTE
     (PORT D (1.92:2.33:2.54) (1.83:2.23:2.43))
     (PORT CLK (4.41:5.35:5.84) (4.51:5.47:5.97))
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     (PORT E (4.36:5.29:5.77) (4.45:5.40:5.89))
  )
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 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (3.09:3.80:4.28))
     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
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     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (SETUP (posedge E) (posedge CLK) (2.34:2.88:3.25))
     (SETUP (negedge E) (posedge CLK) (3.28:4.02:4.54))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
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 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_Second_Buf\[76\])
 (DELAY
  (ABSOLUTE
     (PORT D (6.87:8.33:9.10) (6.59:7.99:8.73))
     (PORT CLK (4.47:5.43:5.93) (4.57:5.54:6.05))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT E (4.45:5.40:5.90) (4.52:5.49:5.99))
  )
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 (TIMINGCHECK 
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     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (SETUP (posedge E) (posedge CLK) (2.34:2.88:3.25))
     (SETUP (negedge E) (posedge CLK) (3.28:4.02:4.54))
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     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
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 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_First_Buf\[49\])
 (DELAY
  (ABSOLUTE
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     (PORT CLK (4.48:5.43:5.93) (4.57:5.54:6.05))
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     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (SETUP (posedge E) (posedge CLK) (2.34:2.88:3.25))
     (SETUP (negedge E) (posedge CLK) (3.28:4.02:4.54))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
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 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_Second_Buf\[77\])
 (DELAY
  (ABSOLUTE
     (PORT D (1.92:2.33:2.54) (1.83:2.23:2.43))
     (PORT CLK (4.37:5.30:5.79) (4.48:5.43:5.93))
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     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
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     (SETUP (negedge E) (posedge CLK) (3.28:4.02:4.54))
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 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_Second_Buf\[68\])
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  (ABSOLUTE
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 (TIMINGCHECK 
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     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (SETUP (posedge E) (posedge CLK) (2.34:2.88:3.25))
     (SETUP (negedge E) (posedge CLK) (3.28:4.02:4.54))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
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 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_Second_Buf\[45\])
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  (ABSOLUTE
     (PORT D (2.00:2.42:2.65) (1.94:2.36:2.58))
     (PORT CLK (4.44:5.39:5.89) (4.53:5.50:6.00))
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 (TIMINGCHECK 
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     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (SETUP (posedge E) (posedge CLK) (2.34:2.88:3.25))
     (SETUP (negedge E) (posedge CLK) (3.28:4.02:4.54))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "OR2")
 (INSTANCE U2\/Data_First_Buf_6_i_a2\[10\])
 (DELAY
  (ABSOLUTE
     (PORT A (4.43:5.37:5.86) (4.51:5.47:5.97))
     (IOPATH A Y (1.96:2.40:2.71) (2.73:3.36:3.79))
     (PORT B (2.32:2.81:3.07) (2.19:2.66:2.90))
     (IOPATH B Y (3.18:3.91:4.41) (3.50:4.30:4.85))
  )
 )
 )
 (CELL
 (CELLTYPE "OR2")
 (INSTANCE U2\/Data_Second_Buf_7_i_a2\[56\])
 (DELAY
  (ABSOLUTE
     (PORT A (4.45:5.40:5.90) (4.52:5.49:5.99))
     (IOPATH A Y (1.96:2.40:2.71) (2.73:3.36:3.79))
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     (IOPATH B Y (3.18:3.91:4.41) (3.50:4.30:4.85))
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 )
 )
 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_First_Buf\[90\])
 (DELAY
  (ABSOLUTE
     (PORT D (1.92:2.33:2.54) (1.83:2.23:2.43))
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 (TIMINGCHECK 
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     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
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     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "OR2")
 (INSTANCE U2\/Data_Second_Buf_7_i_a2\[73\])
 (DELAY
  (ABSOLUTE
     (PORT A (4.33:5.25:5.73) (4.42:5.36:5.85))
     (IOPATH A Y (1.96:2.40:2.71) (2.73:3.36:3.79))
     (PORT B (2.01:2.43:2.66) (1.95:2.37:2.59))
     (IOPATH B Y (3.18:3.91:4.41) (3.50:4.30:4.85))
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 )
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 (CELL
 (CELLTYPE "NOR2A")
 (INSTANCE U2\/Data_Second_Buf_7_0_a2\[87\])
 (DELAY
  (ABSOLUTE
     (PORT A (1.92:2.33:2.54) (1.85:2.25:2.45))
     (IOPATH A Y (3.18:3.91:4.41) (3.40:4.17:4.71))
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 )
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 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_First_Buf\[35\])
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  (ABSOLUTE
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     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
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     (SETUP (negedge E) (posedge CLK) (3.28:4.02:4.54))
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     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_Second_Buf\[101\])
 (DELAY
  (ABSOLUTE
     (PORT D (1.97:2.39:2.61) (1.89:2.29:2.50))
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 (TIMINGCHECK 
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     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
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 )
 )
 (CELL
 (CELLTYPE "OR2")
 (INSTANCE U2\/Data_First_Buf_6_i_a2\[37\])
 (DELAY
  (ABSOLUTE
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 (CELLTYPE "NOR2A")
 (INSTANCE U2\/Data_First_Buf_6_0_a2\[45\])
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  (ABSOLUTE
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 (CELL
 (CELLTYPE "NOR2A")
 (INSTANCE U2\/Data_First_Buf_6_0_a2\[109\])
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  (ABSOLUTE
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 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_First_Buf\[106\])
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  (ABSOLUTE
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 (TIMINGCHECK 
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 (INSTANCE U1\/un6_count_1_I_16)
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  (ABSOLUTE
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     (IOPATH B Y (3.36:4.13:4.66) (3.27:4.01:4.53))
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 (CELLTYPE "IOTRI_OB_EB")
 (INSTANCE DB8_pad\[7\]\/U0\/U1)
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 (INSTANCE U2\/DB8_13_i\[5\])
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 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_Second_Buf\[40\])
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 (TIMINGCHECK 
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     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
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     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))