stdout.log
来自「lcd 1602 xianshi kongzhiqudong」· LOG 代码 · 共 89 行
LOG
89 行
License checkout: synplifypro_asix
Starting: D:\Libero\Synplify\Synplify_862H\bin\mbin\synplify.exe
Install: D:\Libero\Synplify\Synplify_862H
Date: Tue Sep 04 16:40:06 2007
Version: 8.6.2H
Arguments: -pro LCD_Top_syn.prj
ProductType: synplify_pro
License: synplifypro_asix node-locked
Running synthesis on LCD_Top_syn:synthesis
log file: "C:\Actelprj\yan\LCD_1602\synthesis\LCD_Top.srr"
Running Verilog Compiler...
Verilog Compiler Completed
Total: 0 errors, 54 warnings, 10 notes
Running Analysis Property Generator...
Launching mapper in pro mode
Analysis Property Generator Completed
Analysis Property Generator Complete
Total: 0 errors, 54 warnings, 10 notes
Running Fusion Mapper...
Launching mapper in pro mode
Fusion Mapper Completed with warnings
Total: 0 errors, 60 warnings, 16 notes
Running synthesis on LCD_Top_syn:synthesis
log file: "C:\Actelprj\yan\LCD_1602\synthesis\LCD_Top.srr"
Running Verilog Compiler...
Verilog Compiler Completed
Total: 0 errors, 54 warnings, 10 notes
Running Analysis Property Generator...
Launching mapper in pro mode
Analysis Property Generator Completed
Analysis Property Generator Complete
Total: 0 errors, 54 warnings, 10 notes
Running Fusion Mapper...
Launching mapper in pro mode
Fusion Mapper Completed with warnings
Total: 0 errors, 60 warnings, 16 notes
exit status=0
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