📄 lcd_top.srr
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Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------------------------
U2.disp_count[3] DFN1C1 Q Out 0.476 0.476 -
disp_count[3] Net - - 0.463 - 2
U2.state_ns_o2_i_a2_0[6] NOR2A A In - 0.939 -
U2.state_ns_o2_i_a2_0[6] NOR2A Y Out 0.460 1.399 -
state_ns_o2_i_a2_0[6] Net - - 0.275 - 1
U2.state_ns_o2_i_a2[6] OR2B B In - 1.674 -
U2.state_ns_o2_i_a2[6] OR2B Y Out 0.460 2.133 -
N_587 Net - - 1.741 - 10
U2.state_ns_i_a2_i_o2_0[5] OR2B B In - 3.874 -
U2.state_ns_i_a2_i_o2_0[5] OR2B Y Out 0.460 4.334 -
state_ns_i_a2_i_o2_0[5] Net - - 0.463 - 2
U2.state_ns_i_a2_i_o2[5] OR2A A In - 4.796 -
U2.state_ns_i_a2_i_o2[5] OR2A Y Out 0.399 5.196 -
N_478_i_0 Net - - 0.463 - 2
U2.un1_Data_First_Buf_1_sqmuxa_0_a2 OR2A A In - 5.658 -
U2.un1_Data_First_Buf_1_sqmuxa_0_a2 OR2A Y Out 0.399 6.057 -
un1_Data_First_Buf_1_sqmuxa_0_a2 Net - - 0.275 - 1
I_1 CLKINT A In - 6.332 -
I_1 CLKINT Y Out 0.131 6.463 -
I_1 Net - - 2.697 - 98
U2.Data_First_Buf_130_i NOR2B A In - 9.160 -
U2.Data_First_Buf_130_i NOR2B Y Out 0.384 9.543 -
Data_First_Buf_130_i Net - - 0.275 - 1
U2.Data_First_Buf[47] DFN1 D In - 9.818 -
====================================================================================================
Total path delay (propagation time + setup) of 10.228 is 3.578(35.0%) logic and 6.651(65.0%) route.
Path information for path number 4:
Requested Period: 10.000
- Setup time: 0.410
= Required time: 9.590
- Propagation time: 9.752
= Slack (non-critical) : -0.162
Number of logic level(s): 7
Starting point: U2.disp_count[0] / Q
Ending point: U2.Data_First_Buf[47] / D
The start point is clocked by Clock_Gen|clk_BUF_inferred_clock [rising] on pin CLK
The end point is clocked by Clock_Gen|clk_BUF_inferred_clock [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------------------------
U2.disp_count[0] DFN1C1 Q Out 0.382 0.382 -
disp_count[0] Net - - 0.646 - 3
U2.state_ns_o2_i_a2_0[6] NOR2A B In - 1.028 -
U2.state_ns_o2_i_a2_0[6] NOR2A Y Out 0.304 1.332 -
state_ns_o2_i_a2_0[6] Net - - 0.275 - 1
U2.state_ns_o2_i_a2[6] OR2B B In - 1.607 -
U2.state_ns_o2_i_a2[6] OR2B Y Out 0.460 2.066 -
N_587 Net - - 1.741 - 10
U2.state_ns_i_a2_i_o2_0[5] OR2B B In - 3.807 -
U2.state_ns_i_a2_i_o2_0[5] OR2B Y Out 0.460 4.267 -
state_ns_i_a2_i_o2_0[5] Net - - 0.463 - 2
U2.state_ns_i_a2_i_o2[5] OR2A A In - 4.729 -
U2.state_ns_i_a2_i_o2[5] OR2A Y Out 0.399 5.129 -
N_478_i_0 Net - - 0.463 - 2
U2.un1_Data_First_Buf_1_sqmuxa_0_a2 OR2A A In - 5.591 -
U2.un1_Data_First_Buf_1_sqmuxa_0_a2 OR2A Y Out 0.399 5.990 -
un1_Data_First_Buf_1_sqmuxa_0_a2 Net - - 0.275 - 1
I_1 CLKINT A In - 6.265 -
I_1 CLKINT Y Out 0.131 6.396 -
I_1 Net - - 2.697 - 98
U2.Data_First_Buf_130_i NOR2B A In - 9.093 -
U2.Data_First_Buf_130_i NOR2B Y Out 0.384 9.477 -
Data_First_Buf_130_i Net - - 0.275 - 1
U2.Data_First_Buf[47] DFN1 D In - 9.752 -
====================================================================================================
Total path delay (propagation time + setup) of 10.162 is 3.328(32.7%) logic and 6.834(67.3%) route.
Path information for path number 5:
Requested Period: 10.000
- Setup time: 0.310
= Required time: 9.690
- Propagation time: 9.558
= Slack (non-critical) : 0.132
Number of logic level(s): 7
Starting point: U2.state[5] / Q
Ending point: U2.disp_count[3] / D
The start point is clocked by Clock_Gen|clk_BUF_inferred_clock [rising] on pin CLK
The end point is clocked by Clock_Gen|clk_BUF_inferred_clock [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------------
U2.state[5] DFN1C1 Q Out 0.476 0.476 -
state_0[5] Net - - 0.275 - 1
I_3 CLKINT A In - 0.751 -
I_3 CLKINT Y Out 0.131 0.882 -
U2.state[5] Net - - 2.640 - 93
U2.disp_count_9_i_o2[0] OR2 B In - 3.522 -
U2.disp_count_9_i_o2[0] OR2 Y Out 0.474 3.996 -
disp_count_9_i_o2[0] Net - - 1.593 - 9
U2.un1_disp_count_1.I_1 AND2 B In - 5.589 -
U2.un1_disp_count_1.I_1 AND2 Y Out 0.460 6.049 -
DWACT_ADD_CI_0_TMP[0] Net - - 0.463 - 2
U2.un1_disp_count_1.I_19 NOR2B A In - 6.511 -
U2.un1_disp_count_1.I_19 NOR2B Y Out 0.384 6.895 -
DWACT_ADD_CI_0_g_array_1[0] Net - - 0.463 - 2
U2.un1_disp_count_1.I_21 NOR2B A In - 7.357 -
U2.un1_disp_count_1.I_21 NOR2B Y Out 0.384 7.741 -
DWACT_ADD_CI_0_g_array_12[0] Net - - 0.275 - 1
U2.un1_disp_count_1.I_17 XOR2 B In - 8.016 -
U2.un1_disp_count_1.I_17 XOR2 Y Out 0.681 8.696 -
I_17 Net - - 0.275 - 1
U2.disp_count_9_i[3] OA1A C In - 8.971 -
U2.disp_count_9_i[3] OA1A Y Out 0.312 9.283 -
N_24 Net - - 0.275 - 1
U2.disp_count[3] DFN1C1 D In - 9.558 -
=============================================================================================
Total path delay (propagation time + setup) of 9.868 is 3.610(36.6%) logic and 6.258(63.4%) route.
##### END OF TIMING REPORT #####]
--------------------------------------------------------------------------------
Report for cell LCD_Top.verilog
Core Cell usage:
cell count area count*area
DFN1E0 189 1.0 189.0
OR2 106 1.0 106.0
NOR2A 79 1.0 79.0
DFN1C1 21 1.0 21.0
NOR2B 15 1.0 15.0
XOR2 13 1.0 13.0
MX2 10 1.0 10.0
DFN1E0C1 9 1.0 9.0
AND3 8 1.0 8.0
OA1A 6 1.0 6.0
CLKINT 5 0.0 0.0
VCC 4 0.0 0.0
GND 4 0.0 0.0
OR2A 4 1.0 4.0
BUFF 3 1.0 3.0
DFN1P1 3 1.0 3.0
AND2 3 1.0 3.0
NOR3B 3 1.0 3.0
INV 2 1.0 2.0
MX2C 2 1.0 2.0
OR2B 2 1.0 2.0
MX2B 2 1.0 2.0
DFN1 2 1.0 2.0
AO1C 1 1.0 1.0
MX2A 1 1.0 1.0
OA1B 1 1.0 1.0
OR3C 1 1.0 1.0
DFN1E1C1 1 1.0 1.0
PLLINT 1 0.0 0.0
PLL 1 0.0 0.0
----- ----------
TOTAL 502 487.0
IO Cell usage:
cell count
OUTBUF 11
INBUF 2
-----
TOTAL 13
Mapper successful!
Process took 0h:00m:03s realtime, 0h:00m:03s cputime
# Tue Sep 04 16:40:24 2007
###########################################################]
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