📄 lcd_top.srr
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DWACT_FINC_E[0] Net - - 1.161 - 6
U1.un6_count_1.I_48 AND3 A In - 3.123 -
U1.un6_count_1.I_48 AND3 Y Out 0.389 3.511 -
DWACT_FINC_E[4] Net - - 0.275 - 1
U1.un6_count_1.I_51 NOR2B B In - 3.786 -
U1.un6_count_1.I_51 NOR2B Y Out 0.460 4.246 -
N_4 Net - - 0.275 - 1
U1.un6_count_1.I_52 XOR2 A In - 4.521 -
U1.un6_count_1.I_52 XOR2 Y Out 0.313 4.834 -
I_52 Net - - 0.275 - 1
U1.count_5[9] NOR2B A In - 5.109 -
U1.count_5[9] NOR2B Y Out 0.384 5.492 -
count_5[9] Net - - 0.275 - 1
U1.count[9] DFN1C1 D In - 5.767 -
====================================================================================
Total path delay (propagation time + setup) of 6.177 is 2.900(46.9%) logic and 3.277(53.1%) route.
====================================
Detailed Report for Clock: Clock_Gen|clk_BUF_inferred_clock
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
-----------------------------------------------------------------------------------------------------------------
U2.disp_count[1] Clock_Gen|clk_BUF_inferred_clock DFN1C1 Q disp_count[1] 0.476 -0.336
U2.disp_count[2] Clock_Gen|clk_BUF_inferred_clock DFN1C1 Q disp_count[2] 0.476 -0.260
U2.disp_count[3] Clock_Gen|clk_BUF_inferred_clock DFN1C1 Q disp_count[3] 0.476 -0.228
U2.disp_count[0] Clock_Gen|clk_BUF_inferred_clock DFN1C1 Q disp_count[0] 0.382 -0.162
U2.state[5] Clock_Gen|clk_BUF_inferred_clock DFN1C1 Q state_0[5] 0.476 0.132
U2.state[4] Clock_Gen|clk_BUF_inferred_clock DFN1C1 Q state_0[4] 0.382 1.008
U2.state_0[6] Clock_Gen|clk_BUF_inferred_clock DFN1C1 Q state_0[6] 0.476 1.972
U2.state[1] Clock_Gen|clk_BUF_inferred_clock DFN1C1 Q state[1] 0.382 5.989
U2.state[7] Clock_Gen|clk_BUF_inferred_clock DFN1P1 Q state_i_0[7] 0.476 6.120
U2.state[6] Clock_Gen|clk_BUF_inferred_clock DFN1C1 Q state[6] 0.476 6.138
=================================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
------------------------------------------------------------------------------------------------------------------------------
U2.Data_First_Buf[47] Clock_Gen|clk_BUF_inferred_clock DFN1 D Data_First_Buf_130_i 9.590 -0.336
U2.disp_count[3] Clock_Gen|clk_BUF_inferred_clock DFN1C1 D N_24 9.690 0.132
U2.Data_First_Buf[6] Clock_Gen|clk_BUF_inferred_clock DFN1E0 E I_1 9.650 0.383
U2.Data_First_Buf[8] Clock_Gen|clk_BUF_inferred_clock DFN1E0 E I_1 9.650 0.383
U2.Data_First_Buf[9] Clock_Gen|clk_BUF_inferred_clock DFN1E0 E I_1 9.650 0.383
U2.Data_First_Buf[10] Clock_Gen|clk_BUF_inferred_clock DFN1E0 E I_1 9.650 0.383
U2.Data_First_Buf[11] Clock_Gen|clk_BUF_inferred_clock DFN1E0 E I_1 9.650 0.383
U2.Data_First_Buf[14] Clock_Gen|clk_BUF_inferred_clock DFN1E0 E I_1 9.650 0.383
U2.Data_First_Buf[16] Clock_Gen|clk_BUF_inferred_clock DFN1E0 E I_1 9.650 0.383
U2.Data_First_Buf[17] Clock_Gen|clk_BUF_inferred_clock DFN1E0 E I_1 9.650 0.383
==============================================================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 10.000
- Setup time: 0.410
= Required time: 9.590
- Propagation time: 9.926
= Slack (critical) : -0.336
Number of logic level(s): 7
Starting point: U2.disp_count[1] / Q
Ending point: U2.Data_First_Buf[47] / D
The start point is clocked by Clock_Gen|clk_BUF_inferred_clock [rising] on pin CLK
The end point is clocked by Clock_Gen|clk_BUF_inferred_clock [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------------------------
U2.disp_count[1] DFN1C1 Q Out 0.476 0.476 -
disp_count[1] Net - - 0.646 - 3
U2.state_ns_o2_i_a2_1[6] NOR2B B In - 1.122 -
U2.state_ns_o2_i_a2_1[6] NOR2B Y Out 0.460 1.582 -
state_ns_o2_i_a2_1[6] Net - - 0.275 - 1
U2.state_ns_o2_i_a2[6] OR2B A In - 1.857 -
U2.state_ns_o2_i_a2[6] OR2B Y Out 0.384 2.240 -
N_587 Net - - 1.741 - 10
U2.state_ns_i_a2_i_o2_0[5] OR2B B In - 3.982 -
U2.state_ns_i_a2_i_o2_0[5] OR2B Y Out 0.460 4.441 -
state_ns_i_a2_i_o2_0[5] Net - - 0.463 - 2
U2.state_ns_i_a2_i_o2[5] OR2A A In - 4.904 -
U2.state_ns_i_a2_i_o2[5] OR2A Y Out 0.399 5.303 -
N_478_i_0 Net - - 0.463 - 2
U2.un1_Data_First_Buf_1_sqmuxa_0_a2 OR2A A In - 5.765 -
U2.un1_Data_First_Buf_1_sqmuxa_0_a2 OR2A Y Out 0.399 6.165 -
un1_Data_First_Buf_1_sqmuxa_0_a2 Net - - 0.275 - 1
I_1 CLKINT A In - 6.439 -
I_1 CLKINT Y Out 0.131 6.570 -
I_1 Net - - 2.697 - 98
U2.Data_First_Buf_130_i NOR2B A In - 9.267 -
U2.Data_First_Buf_130_i NOR2B Y Out 0.384 9.651 -
Data_First_Buf_130_i Net - - 0.275 - 1
U2.Data_First_Buf[47] DFN1 D In - 9.926 -
====================================================================================================
Total path delay (propagation time + setup) of 10.336 is 3.502(33.9%) logic and 6.834(66.1%) route.
Path information for path number 2:
Requested Period: 10.000
- Setup time: 0.410
= Required time: 9.590
- Propagation time: 9.850
= Slack (non-critical) : -0.260
Number of logic level(s): 7
Starting point: U2.disp_count[2] / Q
Ending point: U2.Data_First_Buf[47] / D
The start point is clocked by Clock_Gen|clk_BUF_inferred_clock [rising] on pin CLK
The end point is clocked by Clock_Gen|clk_BUF_inferred_clock [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------------------------
U2.disp_count[2] DFN1C1 Q Out 0.476 0.476 -
disp_count[2] Net - - 0.646 - 3
U2.state_ns_o2_i_a2_1[6] NOR2B A In - 1.122 -
U2.state_ns_o2_i_a2_1[6] NOR2B Y Out 0.384 1.506 -
state_ns_o2_i_a2_1[6] Net - - 0.275 - 1
U2.state_ns_o2_i_a2[6] OR2B A In - 1.781 -
U2.state_ns_o2_i_a2[6] OR2B Y Out 0.384 2.164 -
N_587 Net - - 1.741 - 10
U2.state_ns_i_a2_i_o2_0[5] OR2B B In - 3.906 -
U2.state_ns_i_a2_i_o2_0[5] OR2B Y Out 0.460 4.365 -
state_ns_i_a2_i_o2_0[5] Net - - 0.463 - 2
U2.state_ns_i_a2_i_o2[5] OR2A A In - 4.828 -
U2.state_ns_i_a2_i_o2[5] OR2A Y Out 0.399 5.227 -
N_478_i_0 Net - - 0.463 - 2
U2.un1_Data_First_Buf_1_sqmuxa_0_a2 OR2A A In - 5.689 -
U2.un1_Data_First_Buf_1_sqmuxa_0_a2 OR2A Y Out 0.399 6.089 -
un1_Data_First_Buf_1_sqmuxa_0_a2 Net - - 0.275 - 1
I_1 CLKINT A In - 6.364 -
I_1 CLKINT Y Out 0.131 6.494 -
I_1 Net - - 2.697 - 98
U2.Data_First_Buf_130_i NOR2B A In - 9.191 -
U2.Data_First_Buf_130_i NOR2B Y Out 0.384 9.575 -
Data_First_Buf_130_i Net - - 0.275 - 1
U2.Data_First_Buf[47] DFN1 D In - 9.850 -
====================================================================================================
Total path delay (propagation time + setup) of 10.260 is 3.426(33.4%) logic and 6.834(66.6%) route.
Path information for path number 3:
Requested Period: 10.000
- Setup time: 0.410
= Required time: 9.590
- Propagation time: 9.818
= Slack (non-critical) : -0.228
Number of logic level(s): 7
Starting point: U2.disp_count[3] / Q
Ending point: U2.Data_First_Buf[47] / D
The start point is clocked by Clock_Gen|clk_BUF_inferred_clock [rising] on pin CLK
The end point is clocked by Clock_Gen|clk_BUF_inferred_clock [rising] on pin CLK
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