lcd_top.srr

lcd 1602 xianshi kongzhiqudong

#Build: Synplify Pro 8.6.2H, Build 017R, Dec  7 2006
#install: D:\Libero\Synplify\Synplify_862H
#OS: Windows XP 5.1
#Hostname: SHOUJINQIAO

#Tue Sep 04 16:40:19 2007

$ Start of Compile
#Tue Sep 04 16:40:19 2007

Synplicity Verilog Compiler, version 3.7, Build 090R, built Nov 17 2006
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved

@I::"D:\Libero\Synplify\Synplify_862H\lib\proasic\fusion.v"
@I::"C:\Actelprj\yan\LCD_1602\smartgen\PLL_1M\PLL_1M.v"
@I::"C:\Actelprj\yan\LCD_1602\hdl\Clock_Gen.v"
@I::"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v"
@I::"C:\Actelprj\yan\LCD_1602\hdl\LCD_Top.v"
Verilog syntax check successful!

Compiler output is up to date.  No re-compile necessary

Selecting top level module LCD_Top
@N: CG364 :"D:\Libero\Synplify\Synplify_862H\lib\proasic\fusion.v":2043:7:2043:9|Synthesizing module VCC

@N: CG364 :"D:\Libero\Synplify\Synplify_862H\lib\proasic\fusion.v":1224:7:1224:9|Synthesizing module GND

@N: CG364 :"D:\Libero\Synplify\Synplify_862H\lib\proasic\fusion.v":2974:7:2974:9|Synthesizing module PLL

@N: CG364 :"D:\Libero\Synplify\Synplify_862H\lib\proasic\fusion.v":260:7:260:12|Synthesizing module PLLINT

@N: CG364 :"C:\Actelprj\yan\LCD_1602\smartgen\PLL_1M\PLL_1M.v":5:7:5:12|Synthesizing module PLL_1M

@N: CG364 :"C:\Actelprj\yan\LCD_1602\hdl\Clock_Gen.v":5:7:5:15|Synthesizing module Clock_Gen

@N: CG179 :"C:\Actelprj\yan\LCD_1602\hdl\Clock_Gen.v":35:27:35:33|Removing redundant assignment
@W: CS148 :"C:\Actelprj\yan\LCD_1602\hdl\Clock_Gen.v":15:12:15:13|Undriven input OADIVRST, tying to 0
@N: CG364 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":7:7:7:16|Synthesizing module LCD_Driver

@W: CL112 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Feedback mux created for signal Data_Second_Buf[111:0]. Did you forget the set/reset assignment for this signal?
@W: CL112 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Feedback mux created for signal Data_First_Buf[111:0]. Did you forget the set/reset assignment for this signal?
@W: CL189 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Register bit Data_First_Buf[3] is always 0, optimizing ...
@W: CL189 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Register bit Data_First_Buf[4] is always 0, optimizing ...
@W: CL189 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Register bit Data_First_Buf[5] is always 0, optimizing ...
@W: CL189 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Register bit Data_First_Buf[7] is always 0, optimizing ...
@W: CL189 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Register bit Data_Second_Buf[1] is always 0, optimizing ...
@W: CL189 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Register bit Data_Second_Buf[4] is always 0, optimizing ...
@W: CL189 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Register bit Data_Second_Buf[7] is always 0, optimizing ...
@W: CL171 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Pruning Register bit <7> of Data_First_Buf[111:0] 

@W: CL171 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Pruning Register bit <5> of Data_First_Buf[111:0] 

@W: CL171 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Pruning Register bit <4> of Data_First_Buf[111:0] 

@W: CL171 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Pruning Register bit <3> of Data_First_Buf[111:0] 

@W: CL171 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Pruning Register bit <7> of Data_Second_Buf[111:0] 

@W: CL171 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Pruning Register bit <4> of Data_Second_Buf[111:0] 

@W: CL171 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Pruning Register bit <1> of Data_Second_Buf[111:0] 

@N: CG364 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Top.v":5:7:5:13|Synthesizing module LCD_Top

@W: CL189 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Register bit Data_First_Buf[12] is always 0, optimizing ...
@W: CL189 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Register bit Data_First_Buf[13] is always 0, optimizing ...
@W: CL189 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Register bit Data_First_Buf[15] is always 0, optimizing ...
@W: CL189 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Register bit Data_Second_Buf[12] is always 0, optimizing ...
@W: CL189 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Register bit Data_Second_Buf[15] is always 0, optimizing ...
@W: CL171 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Pruning Register bit <15> of Data_Second_Buf[111:8] 

@W: CL171 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Pruning Register bit <12> of Data_Second_Buf[111:8] 

@W: CL171 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Pruning Register bit <15> of Data_First_Buf[111:8] 

@W: CL171 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Pruning Register bit <13> of Data_First_Buf[111:8] 

@W: CL171 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Pruning Register bit <12> of Data_First_Buf[111:8] 

@W: CL189 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Register bit Data_Second_Buf[20] is always 0, optimizing ...
@W: CL189 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Register bit Data_Second_Buf[23] is always 0, optimizing ...
@W: CL189 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Register bit Data_First_Buf[21] is always 0, optimizing ...
@W: CL189 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Register bit Data_First_Buf[23] is always 0, optimizing ...
@W: CL171 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Pruning Register bit <23> of Data_First_Buf[111:16] 

@W: CL171 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Pruning Register bit <21> of Data_First_Buf[111:16] 

@W: CL171 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Pruning Register bit <23> of Data_Second_Buf[111:16] 

@W: CL171 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Pruning Register bit <20> of Data_Second_Buf[111:16] 

@W: CL189 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Register bit Data_Second_Buf[28] is always 0, optimizing ...
@W: CL189 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Register bit Data_Second_Buf[31] is always 0, optimizing ...
@W: CL189 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Register bit Data_First_Buf[31] is always 0, optimizing ...
@W: CL171 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Pruning Register bit <31> of Data_First_Buf[111:24] 

@W: CL171 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Pruning Register bit <31> of Data_Second_Buf[111:24] 

@W: CL171 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Pruning Register bit <28> of Data_Second_Buf[111:24] 

@N: CL201 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Trying to extract state machine for register state
Extracted state machine for register state
State machine has 8 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
@W: CL189 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Register bit Data_Second_Buf[39] is always 0, optimizing ...
@W: CL189 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Register bit Data_First_Buf[39] is always 0, optimizing ...
@W: CL171 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Pruning Register bit <39> of Data_First_Buf[111:32] 

@W: CL171 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Pruning Register bit <39> of Data_Second_Buf[111:32] 

@W: CL171 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Pruning Register bit <2> of Data_First_Buf[2:0] 

@W: CL171 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Pruning Register bit <1> of Data_First_Buf[2:0] 

@W: CL171 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Pruning Register bit <6> of Data_Second_Buf[6:5] 

@W: CL171 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Pruning Register bit <3> of Data_Second_Buf[3:2] 

@W: CL171 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Pruning Register bit <14> of Data_Second_Buf[14:13] 

@W: CL171 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Pruning Register bit <11> of Data_Second_Buf[11:8] 

@W: CL171 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Pruning Register bit <22> of Data_Second_Buf[22:21] 

@W: CL171 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Pruning Register bit <19> of Data_Second_Buf[19:16] 

@W: CL171 :"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v":43:0:43:5|Pruning Register bit <27> of Data_Second_Buf[27:24] 

@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Sep 04 16:40:19 2007

###########################################################]
Synplicity Proasic Technology Mapper, Version 9.0.0, Build 368R, Built Nov 27 2006 12:29:38
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved
Product Version Version 8.6.2H
@N: MF249 |Running in 32-bit mode.
@N: MF258 |Gated clock conversion disabled 
@W: BN153 |View "prim", Cell "NGMUX", Port "CLK0": remove clock marking
@W: BN153 |View "prim", Cell "NGMUX", Port "CLK1": remove clock marking
@W: BN154 |View "prim" of Cell "NGMUX": 4 sequential timing arcs are removed


Automatic dissolve at startup in view:work.Clock_Gen(verilog) of U1(PLL_1M)
@W: BN132 :"c:\actelprj\yan\lcd_1602\hdl\lcd_driver.v":43:0:43:5|Removing sequential instance U2.Data_First_Buf[0],  because it is equivalent to instance U2.Data_First_Buf[6]
@W: BN132 :"c:\actelprj\yan\lcd_1602\hdl\lcd_driver.v":43:0:43:5|Removing sequential instance U2.Data_Second_Buf[2],  because it is equivalent to instance U2.Data_Second_Buf[5]
@W: BN132 :"c:\actelprj\yan\lcd_1602\hdl\lcd_driver.v":43:0:43:5|Removing sequential instance U2.Data_Second_Buf[0],  because it is equivalent to instance U2.Data_Second_Buf[5]
RTL optimization done.

Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 43MB peak: 45MB)
@N: MF238 :"c:\actelprj\yan\lcd_1602\hdl\clock_gen.v":36:25:36:37|Found 10 bit incrementor, 'un6_count_1[9:0]'
Encoding state machine work.LCD_Driver(verilog)-state[7:0]
original code -> new code
   0000 -> 00000001
   0001 -> 00000010
   0010 -> 00000100
   0011 -> 00001000
   0100 -> 00010000
   0101 -> 00100000
   0110 -> 01000000
   0111 -> 10000000

Finished factoring (Time elapsed 0h:00m:01s; Memory used current: 45MB peak: 46MB)

Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:01s; Memory used current: 45MB peak: 46MB)

Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:02s; Memory used current: 45MB peak: 46MB)