pll_1m.cxf

lcd 1602 xianshi kongzhiqudong

<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>PLL_1M</name><fileSets><fileSet fileSetId="HDL_FILESET"><file fileId="1"><name>PLL_1M.v</name><fileType>verilogSource</fileType></file></fileSet><fileSet fileSetId="OTHER_FILESET"><file fileId="2"><name>PLL_1M.gen</name><fileType><userFileType type="GEN"/></fileType></file><file fileId="3"><name>PLL_1M.log</name><fileType><userFileType type="LOG"/></fileType></file></fileSet></fileSets><views><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view><view><fileSetRef>OTHER_FILESET</fileSetRef><name>Other</name></view></views><category>Clock Conditioning / PLL</category><function>Static PLL</function><variation>Static PLL</variation><vendor>Actel</vendor><version>2.1</version><model><signals><signal><name>POWERDOWN</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad></vendorExtensions></signal><signal><name>CLKA</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad></vendorExtensions></signal><signal><name>LOCK</name><direction>out</direction><export>false</export><vendorExtensions><pad>false</pad></vendorExtensions></signal><signal><name>GLA</name><direction>out</direction><export>false</export><vendorExtensions><pad>false</pad></vendorExtensions></signal><signal><name>OADIVRST</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad></vendorExtensions></signal></signals></model></Component>