pll_1m.log

lcd 1602 xianshi kongzhiqudong

 ** Message System Log
 ** Database: 
 ** Date:   Mon Aug 27 18:19:55 2007


****************
Macro Parameters
****************

Name                            : PLL_1M
Family                          : Fusion
Output Format                   : VERILOG
Type                            : Static PLL
PowerDown                       : Active Low
Lock                            : Active High
Input Freq(Mhz)                 : 48.000000
CLKA Source                     : External I/O
Feedback Delay Value Index      : 1
Feedback Mux Select             : 1
XDLY Mux Select                 : No
Primary Freq(Mhz)               : 1.000000
Primary PhaseShift              : 0
Primary Delay Value Index       : 1
Primary Mux Select              : 4
Secondary1 Freq(Mhz)            : 0.000000
Use GLB                         : NO
Use YB                          : NO
GLB Delay Value Index           : 32
YB Delay Value Index            : 32
Secondary1 PhaseShift           : 0
Secondary1 Mux Select           : 0
Secondary2 Freq(Mhz)            : 0.000000
Use GLC                         : NO
Use YC                          : NO
GLC Delay Value Index           : 32
YC Delay Value Index            : 32
Secondary2 PhaseShift           : 0
Secondary2 Mux Select           : 0

Configuration Bits:
FINDIV[6:0]     0001000
FBDIV[6:0]      0000101
OADIV[4:0]      11111
OADIVHALF       0
OBDIV[4:0]      00000
OCDIV[4:0]      00000
OAMUX[2:0]      100
OBMUX[2:0]      000
OCMUX[2:0]      000
FBSEL[1:0]      01
FBDLY[4:0]      00000
XDLYSEL         0
DLYGLA[4:0]     00000
DLYGLB[4:0]     00000
DLYGLC[4:0]     00000
DLYYB[4:0]      00000
DLYYC[4:0]      00000
VCOSEL[2:0]     000


Primary Clock Frequency 1.000
Primary Clock Phase Shift 0.000
Primary Clock Output Delay from CLKA 1.695


**************
Compile Report
**************


Netlist Resource Report
=======================

    CORE                     Used:      0
    IO (W/ clocks)           Used:      0
    Low Static ICC           Used:      0
    FlashROM                 Used:      0
    User JTAG                Used:      0
    RC oscillator            Used:      0
    XTL oscillator           Used:      0
    NVM                      Used:      0
    AB                       Used:      0
    AnalogIO                 Used:      0
    VRPSM                    Used:      0
    No-Glitch MUX            Used:      0

Written Verilog netlist to C:/Actel_lab/LCD_1602/smartgen\PLL_1M\PLL_1M.v.

 ** Log Ended:   Mon Aug 27 18:19:57 2007