my_or.1

verilog 或门程序 初学者必备。。。。。。。。。。。。

V 50
K _ my_or
Y 1
D 0 0 90 100
Z 10
i 9
P 1 0 60 20 60 0 2 0
L 20 60 10 0 2 0 1 0 A
A 0 70 10 0 2 0 PINTYPE=IN
P 2 0 40 20 40 0 2 0
L 20 40 10 0 2 0 1 0 B
A 0 50 10 0 2 0 PINTYPE=IN
P 3 90 60 70 60 0 3 0
L 60 60 10 0 2 0 1 0 Y
A 70 70 10 0 2 0 PINTYPE=OUT
U 20 10 10 0 2 3 DEVICE=my_or
U 20 0 10 0 3 0 VFILE=E:/work/EasyFPGA030/my_or/component/work/my_or/my_or.v
U 20 -10 10 0 3 0 ACCEL=VCS
U 20 -20 10 0 3 0 LEVEL=VERILOG
U 20 -30 10 0 3 0 VERILOG=my_or
U 20 -40 10 0 3 0 PINORDER=A B Y 
b 20 20 70 80
E