📄 makefile
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################################################################################# Automatically-generated file. Do not edit!################################################################################-include ../makefile.initRM := rm -rf# All of the sources participating in the build are defined here-include sources.mk-include subdir.mk-include objects.mkifneq ($(MAKECMDGOALS),clean)ifneq ($(strip $(C_DEPS)),)-include $(C_DEPS)endifendif-include ../makefile.defs# Add inputs and outputs from these tool invocations to the build variables # All Targetall: proc_module# Tool invocationsproc_module: $(OBJS) $(USER_OBJS) @echo 'Building target: $@' @echo 'Invoking: GCC C Linker' gcc -o"proc_module" $(OBJS) $(USER_OBJS) $(LIBS) @echo 'Finished building target: $@' @echo ' '# Other Targetsclean: -$(RM) $(OBJS)$(C_DEPS)$(EXECUTABLES) proc_module -@echo ' '.PHONY: all clean dependents.SECONDARY:-include ../makefile.targets
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