⭐ 欢迎来到虫虫下载站！ | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站
📤 上传资源

📄 12.5fenpin.txt

📁 时钟产生电路
💻 TXT
字号:
🔍 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CLKGEN IS
PORT(CLK:IN STD_LOGIC;
     NEWCLK:OUT STD_LOGIC);
END ENTITY CLKGEN;
ARCHITECTURE ART OF CLKGEN IS
SIGNAL P,Q:INTEGER RANGE 0 TO 24;
BEGIN
  PROCESS(CLK) IS
    BEGIN
      IF(CLK'EVENT AND CLK='1') THEN
        IF P=24 THEN P<=0;
        ELSE P<=P+1;
        END IF;
      END IF;
  END PROCESS;
  PROCESS(CLK) IS
    BEGIN
      IF(CLK'EVENT AND CLK='0') THEN
         IF Q=24 THEN Q<=0;
         ELSE Q<=Q+1;
         END IF;
      END IF;
  END PROCESS;
  NEWCLK<='1' WHEN P=0 OR Q=12 ELSE '0';
END ARCHITECTURE ART;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SPEAKER IS
	PORT(CK4MHZ:IN STD_LOGIC;
		 YINFU:IN INTEGER RANGE 0 TO 14;
		 SP:OUT STD_LOGIC);
END SPEAKER;
ARCHITECTURE ART OF SPEAKER IS
SIGNAL COUNT:INTEGER:=0;
SIGNAL F,TWO:STD_LOGIC;
BEGIN
	PROCESS(YINFU,CK4MHZ)
	BEGIN
		IF(CK4MHZ'EVENT AND CK4MHZ='1')THEN
			IF(YINFU=0) THEN F<='0';
			ELSIF(YINFU=1) THEN COUNT<=COUNT+1;
				IF(COUNT<7644)THEN F<='0';
				ELSE F<='1';COUNT<=0;
				END IF;
			ELSIF(YINFU=2)THEN COUNT<=COUNT+1;
				IF(COUNT<6810)THEN F<='0';
				ELSE F<='1';COUNT<=0;
				END IF;
			ELSIF(YINFU=3)THEN COUNT<=COUNT+1;
				IF(COUNT<6068)THEN F<='0';
				ELSE F<='1';COUNT<=0;
				END IF;
			ELSIF(YINFU=4)THEN COUNT<=COUNT+1;
				IF(COUNT<5726)THEN F<='0';
				ELSE F<='1';COUNT<=0;
				END IF;
			ELSIF(YINFU=5)THEN COUNT<=COUNT+1;
				IF(COUNT<5102)THEN F<='0';
				ELSE F<='1';COUNT<=0;
				END IF;
			ELSIF(YINFU=6)THEN COUNT<=COUNT+1;
				IF(COUNT<4546)THEN F<='0';
				ELSE F<='1';COUNT<=0;
				END IF;
			ELSIF(YINFU=7)THEN COUNT<=COUNT+1;
				IF(COUNT<4050)THEN F<='0';
				ELSE F<='1';COUNT<=0;
				END IF;
			ELSIF(YINFU=8)THEN COUNT<=COUNT+1;
				IF(COUNT<3822)THEN F<='0';
				ELSE F<='1';COUNT<=0;
				END IF;
			ELSIF(YINFU=9)THEN COUNT<=COUNT+1;
				IF(COUNT<3406)THEN F<='0';
				ELSE F<='1';COUNT<=0;
				END IF;
			ELSIF(YINFU=10)THEN COUNT<=COUNT+1;
				IF(COUNT<3034)THEN F<='0';
				ELSE F<='1';COUNT<=0;
				END IF;
			ELSIF(YINFU=11)THEN COUNT<=COUNT+1;
				IF(COUNT<2864)THEN F<='0';
				ELSE F<='1';COUNT<=0;
				END IF;
			ELSIF(YINFU=12)THEN COUNT<=COUNT+1;
				IF(COUNT<2552)THEN F<='0';
				ELSE F<='1';COUNT<=0;
				END IF;
			ELSIF(YINFU=13)THEN COUNT<=COUNT+1;
				IF(COUNT<2272)THEN F<='0';
				ELSE F<='1';COUNT<=0;
				END IF;
			ELSIF(YINFU=14)THEN COUNT<=COUNT+1;
				IF(COUNT<2024)THEN F<='0';
				ELSE F<='1';COUNT<=0;
				END IF;
			END IF;
		END IF;
	END PROCESS;
	PROCESS(F)
	BEGIN
		IF(F'EVENT AND F='1')THEN TWO<=NOT TWO;---输出之前的二分频
		END IF;
		SP<=TWO;
	END PROCESS;
END ART;

library ieee;
use ieee.std_logic_1164.all;
entity yinfu is
port(ck4hz:in std_logic;
	 yf:out integer range 0 to 14);
end yinfu;
architectrue name of yinfu is
signal count:integer:=0;
begin
process(ck4hz)
begin
	if(ck4hz'event and ck4hz='1')then
		if(count<124)then count<=count+1;
		else count<=0;
		end if;
	end if;
end process;
process(count)
begin
	case count is
		when 00=>yf<=0;
		when 01=>yf<=0;
		when 02=>yf<=8;
		when 03=>yf<=8;
		when 04=>yf<=8;
		when 05=>yf<=8;
		when 06=>yf<=7;
		when 07=>yf<=7;
		when 08=>yf<=0;
		when 09=>yf<=0;
		when 10=>yf<=0;
		when 11=>yf<=0;
		when 12=>yf<=8;
		when 13=>yf<=8;
		when 14=>yf<=8;
		when 15=>yf<=8;
		when 16=>yf<=7;
		when 17=>yf<=7;
		when 18=>yf<=7;
		when 19=>yf<=7;
		when 20=>yf<=7;
		when 21=>yf<=12;
		when 22=>yf<=12;
		when 23=>yf<=12;
		when 24=>yf<=12;
		when 25=>yf<=7;
		when 26=>yf<=7;
		when 27=>yf<=7;
		when 28=>yf<=7;
		when 29=>yf<=7;
		when 30=>yf<=7;
		when 31=>yf<=0;
		when 32=>yf<=0;
		when 33=>yf<=6;
		when 34=>yf<=6;
		when 35=>yf<=8;
		when 36=>yf<=8;
		when 37=>yf<=6;
		when 38=>yf<=6;
		when 39=>yf<=8;
		when 40=>yf<=8;
		when 41=>yf<=8;
		when 42=>yf<=8;
		when 43=>yf<=8;
		when 44=>yf<=8;
		when 45=>yf<=8;
		when 46=>yf<=8;
		when 47=>yf<=10;
		when 48=>yf<=10;
		when 49=>yf<=10;
		when 50=>yf<=10;
		when 51=>yf<=9;
		when 52=>yf<=8;
		when 53=>yf<=8;
		when 54=>yf<=8;
		when 55=>yf<=8;
		when 56=>yf<=9;
		when 57=>yf<=9;
		when 58=>yf<=9;
		when 59=>yf<=9;
		when 60=>yf<=9;
		when 61=>yf<=9;
		when 62=>yf<=0;
		when 63=>yf<=0;
		when 64=>yf<=8;
		when 65=>yf<=8;
		when 66=>yf<=8;
		when 67=>yf<=8;
		when 68=>yf<=8;
		when 69=>yf<=8;
		when 70=>yf<=0;
		when 71=>yf<=0;
		when 72=>yf<=0;
		when 73=>yf<=0;
		when 74=>yf<=0;
		when 75=>yf<=0;
		when 76=>yf<=8;
		when 77=>yf<=8;
		when 78=>yf<=7;
		when 79=>yf<=7;
		when 80=>yf<=7;
		when 81=>yf<=7;
		when 82=>yf<=7;
		when 83=>yf<=12;
		when 84=>yf<=12;
		when 85=>yf<=12;
		when 86=>yf<=12;
		when 87=>yf<=7;
		when 88=>yf<=7;
		when 89=>yf<=7;
		when 90=>yf<=7;
		when 91=>yf<=7;
		when 92=>yf<=7;
		when 93=>yf<=0;
		when 94=>yf<=0;
		when 95=>yf<=6;
		when 96=>yf<=6;
		when 97=>yf<=8;
		when 98=>yf<=8;
		when 99=>yf<=6;	
		when 100=>yf<=6;
		when 101=>yf<=8;
		when 102=>yf<=8;
		when 103=>yf<=8;
		when 104=>yf<=8;
		when 105=>yf<=8;
		when 106=>yf<=8;
		when 107=>yf<=6;
		when 108=>yf<=6;
		when 109=>yf<=9;
		when 110=>yf<=9;
		when 111=>yf<=9;
		when 112=>yf<=9;
		when 113=>yf<=9;
		when 114=>yf<=9;
		when 115=>yf<=8;
		when 116=>yf<=8;
		when 117=>yf<=8;
		when 118=>yf<=8;
		when 119=>yf<=9;
		when 120=>yf<=10;
		when 121=>yf<=9;
		when 122=>yf<=9;
		when 123=>yf<=8;
		when 124=>yf<=8;
		when others=>null;
	end case;
end process;
end name;

④键盘扫描：
时钟分频源程序：
library ieee;
use ieee.std_logic_1164.all;
entity kbfq is
port(		clk		:in std_logic;                    --50MHZ
     		newclk	:out std_logic);                  --20HZ
end entity kbfq;
architecture art of kbfq is
signal cnt:integer range 0 to 2499999;
signal newclk_a:std_logic;
  begin
    process(clk) is
    begin
      if(clk'event and clk='1') then
         if cnt=2499999 then cnt<=0;newclk_a<=not newclk_a;
         else cnt<=cnt+1;
         end if;
      end if;
    end process;
    newclk<=newclk_a;
end architecture art;

4*4键盘扫描源程序：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity kb4_4 is
port(clk		:in std_logic;
     kbcol		:in std_logic_vector(3 downto 0);          --列
     kbrow		:out std_logic_vector(3 downto 0);         --行
     kb_out		:out std_logic_vector(13 downto 0));
end entity kb4_4;
architecture art of kb4_4 is
signal count:std_logic_vector(1 downto 0);
signal sta:std_logic_vector(1 downto 0);
begin
  process(clk)
  begin
    if(clk'event and clk='1') then count<=count+1;
    end if;
  end process;
  process(clk)
  begin
    if(clk'event and clk='1') then
       case count is
       when "00" =>kbrow<="0111";sta<="00";
       when "01" =>kbrow<="1011";sta<="01";
       when "10" =>kbrow<="1101";sta<="10";
       when "11" =>kbrow<="1110";sta<="11";
       when others=>kbrow<="0000";
       end case;
    end if;
  end process;
  process(clk)
  begin
    if(clk'event and clk='1') then
       case sta is
       when "00"=>
            case kbcol is
              when "0111"=>kb_out<="00000000001000";     --4
              when "1011"=>kb_out<="00000000000100";     --3
              when "1101"=>kb_out<="00000000000010";     --2
              when "1110"=>kb_out<="00000000000001";     --1
              when others=>kb_out<="00000000000000";
            end case;
       when "01"=>
            case kbcol is
              when "1011"=>kb_out<="00000001000000";      --7
              when "1101"=>kb_out<="00000000100000";      --6
              when "1110"=>kb_out<="00000000010000";      --5
              when others=>kb_out<="00000000000000";
            end case;
       when "10"=>
            case kbcol is
              when "0111"=>kb_out<="00010000000000";      --11
              when "1011"=>kb_out<="00001000000000";      --10
              when "1101"=>kb_out<="00000100000000";      --9
              when "1110"=>kb_out<="00000010000000";      --8
              when others=>kb_out<="00000000000000";
            end case;
       when "11"=>
            case kbcol is
              when "1101"=>kb_out<="10000000000000";       --14
              when "1110"=>kb_out<="01000000000000";       --13
              when "1011"=>kb_out<="00100000000000";       --12
              when others=>kb_out<="00000000000000";
            end case;
       when others=>kb_out<="00000000000000";
       end case;  
    end if;
  end process;
end architecture art;

主程序：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity kb is
port(  	clk       	:in std_logic;
       	kbcol     	:in std_logic_vector(3 downto 0);               
       	kbrow    	:out std_logic_vector(3 downto 0);              
      		seg7_out  	:out std_logic_vector(6 downto 0);
      		kb_out    	:out std_logic_vector(11 downto 0));
end entity kb;
architecture art of kb is
component kbfq is
port(		clk			:in std_logic;
     		newclk		:out std_logic);
end component kbfq;
component kb4_4 is
port(		clk			:in std_logic;
     		kbcol		:in std_logic_vector(3 downto 0);
     		kbrow		:out std_logic_vector(3 downto 0);
     		seg7_out	:out std_logic_vector(6 downto 0);
     		kb_out		:out std_logic_vector(11 downto 0));
end component kb4_4;
signal s0:std_logic;
begin
  u1:kbfq port map(	clk			=>clk,
newclk		=>s0);
  u2:kb4_4 port map(	clk			=>s0,
kbcol		=>kbcol,
kbrow		=>kbrow,
seg7_out		=>seg7_out,
                    kb_out		=>kb_out);
end architecture art;

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -