📄 traffic.rpt
字号:
114 - - - 06 OUTPUT 0 1 0 0 green2
98 - - B -- OUTPUT 0 1 0 0 green3
90 - - D -- OUTPUT 0 1 0 0 green4
87 - - E -- OUTPUT 0 1 0 0 green5
89 - - D -- OUTPUT 0 1 0 0 green6
95 - - C -- OUTPUT 0 1 0 0 green7
99 - - B -- OUTPUT 0 1 0 0 green8
36 - - - 36 OUTPUT 0 1 0 0 green9
33 - - F -- OUTPUT 0 1 0 0 green10
29 - - E -- OUTPUT 0 1 0 0 green11
31 - - F -- OUTPUT 0 1 0 0 green12
30 - - F -- OUTPUT 0 1 0 0 green13
63 - - - 11 OUTPUT 0 1 0 0 green14
68 - - - 07 OUTPUT 0 1 0 0 green15
73 - - - 01 OUTPUT 0 1 0 0 green16
133 - - - 28 OUTPUT 0 1 0 0 out0
140 - - - 32 OUTPUT 0 1 0 0 out1
135 - - - 29 OUTPUT 0 1 0 0 out2
136 - - - 30 OUTPUT 0 1 0 0 out3
141 - - - 33 OUTPUT 0 1 0 0 out4
138 - - - 31 OUTPUT 0 1 0 0 out5
80 - - F -- OUTPUT 0 1 0 0 red1
100 - - A -- OUTPUT 0 1 0 0 red2
102 - - A -- OUTPUT 0 1 0 0 red3
96 - - C -- OUTPUT 0 1 0 0 red4
83 - - E -- OUTPUT 0 1 0 0 red5
91 - - D -- OUTPUT 0 1 0 0 red6
97 - - C -- OUTPUT 0 1 0 0 red7
101 - - A -- OUTPUT 0 1 0 0 red8
32 - - F -- OUTPUT 0 1 0 0 red9
27 - - E -- OUTPUT 0 1 0 0 red10
65 - - - 09 OUTPUT 0 1 0 0 red11
81 - - F -- OUTPUT 0 1 0 0 red12
28 - - E -- OUTPUT 0 1 0 0 red13
70 - - - 05 OUTPUT 0 1 0 0 red14
79 - - F -- OUTPUT 0 1 0 0 red15
78 - - F -- OUTPUT 0 1 0 0 red16
51 - - - 20 OUTPUT 0 1 0 0 row1
59 - - - 16 OUTPUT 0 1 0 0 row2
60 - - - 15 OUTPUT 0 1 0 0 row3
48 - - - 24 OUTPUT 0 1 0 0 row4
46 - - - 27 OUTPUT 0 1 0 0 row5
43 - - - 30 OUTPUT 0 1 0 0 row6
41 - - - 31 OUTPUT 0 1 0 0 row7
38 - - - 34 OUTPUT 0 1 0 0 row8
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\traffic\traffic.rpt
traffic
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - D 19 DFFE + 0 2 0 9 |count2to0:12|lpm_counter:lpm_counter_component|f8count:p8c0|QC (|count2to0:12|lpm_counter:lpm_counter_component|f8count:p8c0|:6)
- 1 - D 34 DFFE + 0 1 0 10 |count2to0:12|lpm_counter:lpm_counter_component|f8count:p8c0|QB (|count2to0:12|lpm_counter:lpm_counter_component|f8count:p8c0|:7)
- 1 - D 32 DFFE + 0 0 0 11 |count2to0:12|lpm_counter:lpm_counter_component|f8count:p8c0|QA (|count2to0:12|lpm_counter:lpm_counter_component|f8count:p8c0|:8)
- 1 - D 03 DFFE + 0 1 0 3 |count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c0|QH (|count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c0|:1)
- 8 - D 09 DFFE + 0 3 0 1 |count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c0|QG (|count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c0|:2)
- 7 - D 09 DFFE + 0 2 0 2 |count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c0|QF (|count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c0|:3)
- 6 - D 09 DFFE + 0 1 0 3 |count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c0|QE (|count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c0|:4)
- 4 - D 09 DFFE + 0 3 0 1 |count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c0|QD (|count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c0|:5)
- 3 - D 09 DFFE + 0 2 0 2 |count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c0|QC (|count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c0|:6)
- 1 - D 09 DFFE + 0 1 0 3 |count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c0|QB (|count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c0|:7)
- 2 - D 11 DFFE + 0 0 0 4 |count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c0|QA (|count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c0|:8)
- 5 - D 09 AND2 0 4 0 4 |count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c0|:291
- 2 - D 09 AND2 0 4 0 4 |count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c0|:297
- 4 - D 13 DFFE + 0 3 0 1 |count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c1|QH (|count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c1|:1)
- 3 - D 13 DFFE + 0 2 0 2 |count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c1|QG (|count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c1|:2)
- 1 - D 13 DFFE + 0 1 0 3 |count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c1|QF (|count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c1|:3)
- 8 - D 03 DFFE + 0 3 0 1 |count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c1|QE (|count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c1|:4)
- 7 - D 03 DFFE + 0 2 0 2 |count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c1|QD (|count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c1|:5)
- 6 - D 03 DFFE + 0 1 0 3 |count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c1|QC (|count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c1|:6)
- 4 - D 03 DFFE + 0 3 0 1 |count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c1|QB (|count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c1|:7)
- 3 - D 03 DFFE + 0 2 0 2 |count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c1|QA (|count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c1|:8)
- 5 - D 03 AND2 0 4 0 4 |count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c1|:287
- 2 - D 03 AND2 0 4 0 4 |count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c1|:293
- 2 - D 13 AND2 0 4 0 4 |count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c1|:299
- 2 - D 15 DFFE + 0 3 0 38 |count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c2|QF (|count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c2|:3)
- 7 - D 15 DFFE + 0 2 0 1 |count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c2|QE (|count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c2|:4)
- 6 - D 15 DFFE + 0 1 0 2 |count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c2|QD (|count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c2|:5)
- 4 - D 15 DFFE + 0 3 0 1 |count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c2|QC (|count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c2|:6)
- 3 - D 15 DFFE + 0 2 0 2 |count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c2|QB (|count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c2|:7)
- 1 - D 15 DFFE + 0 1 0 3 |count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c2|QA (|count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c2|:8)
- 5 - D 15 AND2 0 4 0 3 |count4MHz:3|lpm_counter:lpm_counter_component|f8count:p8c2|:289
- 2 - A 06 DFFE + 0 0 0 11 |count6:124|lpm_counter:lpm_counter_component|dffs0
- 2 - A 29 DFFE + 0 2 0 9 |count6:124|lpm_counter:lpm_counter_component|dffs1
- 1 - A 06 DFFE + 0 2 0 10 |count6:124|lpm_counter:lpm_counter_component|dffs2
- 4 - B 12 DFFE 1 1 0 18 |count24:134|counter0
- 8 - A 35 DFFE 0 3 0 16 |count24:134|counter1
- 4 - A 35 DFFE 0 3 0 17 |count24:134|counter2
- 2 - A 35 DFFE 0 3 0 11 |count24:134|counter3
- 1 - A 35 DFFE 0 4 0 10 |count24:134|counter4
- 1 - A 28 OR2 s 0 2 0 10 |count24:134|~46~1
- 7 - A 35 OR2 1 2 0 4 |count24:134|:51
- 6 - A 35 OR2 ! 0 2 0 3 |count24:134|:58
- 5 - A 35 OR2 ! 0 2 0 9 |count24:134|:62
- 7 - A 29 OR2 ! 0 4 0 4 |digselector:140|:68
- 3 - A 29 OR2 ! 0 4 0 3 |digselector:140|:78
- 3 - A 19 OR2 0 4 0 1 |digselector:140|:87
- 1 - A 29 OR2 ! 0 4 0 4 |digselector:140|:96
- 5 - A 29 OR2 ! 0 4 0 3 |digselector:140|:116
- 3 - A 23 OR2 ! 0 3 0 1 |digselector:140|:128
- 7 - A 31 OR2 0 4 1 0 |digselector:140|:177
- 2 - A 27 OR2 0 4 1 0 |digselector:140|:189
- 2 - A 31 OR2 0 4 1 0 |digselector:140|:190
- 2 - A 30 OR2 0 4 1 0 |digselector:140|:191
- 4 - A 29 OR2 0 4 1 0 |digselector:140|:192
- 4 - A 33 OR2 0 4 1 0 |digselector:140|:193
- 7 - A 26 OR2 s 0 4 0 1 |digselector:140|~195~1
- 3 - A 26 AND2 s 0 4 0 1 |digselector:140|~195~2
- 2 - A 32 OR2 s 0 3 0 1 |digselector:140|~195~3
- 1 - A 32 AND2 s 0 4 0 2 |digselector:140|~195~4
- 6 - A 29 OR2 s 0 4 0 7 |digselector:140|~195~5
- 8 - A 29 OR2 s 0 4 0 7 |digselector:140|~195~6
- 3 - A 31 OR2 s 0 3 0 5 |digselector:140|~195~7
- 5 - A 31 OR2 s 0 4 0 1 |digselector:140|~195~8
- 6 - A 31 OR2 s 0 4 0 1 |digselector:140|~195~9
- 8 - A 31 OR2 s 0 4 0 1 |digselector:140|~195~10
- 1 - A 31 OR2 ! 0 4 0 9 |digselector:140|:195
- 2 - A 01 OR2 s ! 0 3 0 1 |digselector:140|~197~1
- 5 - A 30 OR2 s ! 0 4 0 1 |digselector:140|~197~2
- 6 - A 30 OR2 s ! 0 4 0 1 |digselector:140|~197~3
- 8 - A 30 OR2 s ! 0 4 0 1 |digselector:140|~197~4
- 3 - A 30 OR2 0 4 0 9 |digselector:140|:197
- 1 - A 30 OR2 s 0 4 0 1 |digselector:140|~199~1
- 5 - A 34 OR2 0 4 0 7 |digselector:140|:199
- 7 - A 23 OR2 s 0 4 0 1 |digselector:140|~201~1
- 2 - A 23 OR2 ! 0 4 0 6 |digselector:140|:201
- 6 - D 19 AND2 s 0 3 0 3 |disp:141|~74~1
- 8 - D 34 AND2 s 0 3 0 4 |disp:141|~95~1
- 5 - D 34 AND2 s 0 3 0 2 |disp:141|~117~1
- 2 - D 34 AND2 s 0 3 0 4 |disp:141|~139~1
- 3 - D 19 AND2 s 0 3 0 6 |disp:141|~161~1
- 4 - A 16 AND2 0 2 0 1 |disp:141|:227
- 8 - D 23 AND2 0 3 0 6 |disp:141|:610
- 7 - D 28 AND2 0 2 0 3 |disp:141|:797
- 3 - D 28 AND2 0 4 0 3 |disp:141|:1179
- 5 - D 28 AND2 0 4 0 4 |disp:141|:1373
- 2 - D 28 AND2 0 4 0 4 |disp:141|:1561
- 3 - D 23 AND2 0 2 0 5 |disp:141|:1562
- 2 - D 23 OR2 s 0 4 0 3 |disp:141|~1753~1
- 4 - D 19 AND2 0 4 1 1 |disp:141|:1753
- 3 - D 30 OR2 s 0 4 0 2 |disp:141|~1776~1
- 5 - D 19 OR2 s 0 2 0 2 |disp:141|~1776~2
- 5 - A 16 OR2 s 0 4 0 4 |disp:141|~1776~3
- 6 - D 30 AND2 s 0 2 0 3 |disp:141|~1776~4
- 2 - D 16 OR2 0 2 1 1 |disp:141|:1776
- 6 - A 16 OR2 s 0 3 0 6 |disp:141|~1799~1
- 6 - D 28 OR2 s 0 3 0 2 |disp:141|~1799~2
- 7 - D 07 OR2 s 0 3 0 2 |disp:141|~1799~3
- 4 - D 07 AND2 s 0 2 0 1 |disp:141|~1799~4
- 3 - A 16 OR2 0 3 1 1 |disp:141|:1799
- 5 - D 23 OR2 0 4 1 1 |disp:141|:1823
- 8 - D 28 OR2 s 0 4 0 2 |disp:141|~1846~1
- 4 - D 28 OR2 0 4 1 1 |disp:141|:1846
- 5 - D 18 AND2 s 0 2 0 1 |disp:141|~1870~1
- 1 - D 30 OR2 0 3 1 1 |disp:141|:1870
- 4 - D 32 AND2 0 4 1 1 |disp:141|:1894
- 3 - D 34 AND2 0 4 1 1 |disp:141|:1919
- 4 - D 16 OR2 s 0 2 0 23 |disp:141|~1922~1
- 4 - D 34 OR2 s 0 4 0 4 |disp:141|~1922~2
- 5 - D 05 OR2 s 0 4 0 2 |disp:141|~1922~3
- 5 - D 30 OR2 s 0 4 0 2 |disp:141|~1923~1
- 4 - D 18 OR2 0 4 0 2 |disp:141|:1923
- 1 - D 28 OR2 s 0 4 0 5 |disp:141|~1924~1
- 7 - D 34 OR2 s 0 3 0 2 |disp:141|~1924~2
- 6 - D 34 OR2 s 0 4 0 25 |disp:141|~1924~3
- 7 - D 19 AND2 s 0 4 0 2 |disp:141|~1924~4
- 7 - D 30 OR2 s 0 3 0 3 |disp:141|~1924~5
- 1 - D 16 OR2 s 0 2 0 1 |disp:141|~1924~6
- 4 - D 30 OR2 s 0 4 0 1 |disp:141|~1924~7
- 2 - D 19 OR2 0 4 0 2 |disp:141|:1924
- 8 - D 30 OR2 s 0 3 0 2 |disp:141|~1925~1
- 8 - D 19 AND2 s 0 2 0 1 |disp:141|~1925~2
- 2 - D 30 OR2 0 4 0 2 |disp:141|:1925
- 4 - D 23 OR2 s 0 4 0 3 |disp:141|~1926~1
- 1 - D 23 OR2 s 0 3 0 3 |disp:141|~1926~2
- 2 - D 05 OR2 s 0 4 0 3 |disp:141|~1926~3
- 3 - D 07 OR2 s 0 4 0 2 |disp:141|~1926~4
- 5 - D 07 OR2 s 0 4 0 2 |disp:141|~1926~5
- 5 - B 02 DFFE 1 1 0 3 |hourcount:37|count0
- 8 - B 02 DFFE 1 3 0 2 |hourcount:37|count1
- 7 - B 09 DFFE 0 3 0 3 |hourcount:37|count2
- 6 - B 09 DFFE 0 4 0 2 |hourcount:37|count3
- 5 - B 09 DFFE 0 3 0 2 |hourcount:37|count4
- 8 - B 09 DFFE 0 4 0 1 |hourcount:37|count5
- 2 - B 02 DFFE 1 2 0 4 |hourcount:37|hourcount0
- 3 - B 16 DFFE 0 3 0 3 |hourcount:37|hourcount1
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