📄 traffic.rpt
字号:
RESERVED | 21 88 | green1
RESERVED | 22 87 | green5
RESERVED | 23 86 | RESERVED
VCCIO | 24 85 | VCCINT
GND | 25 84 | GND
RESERVED | 26 83 | red5
red10 | 27 82 | RESERVED
red13 | 28 81 | red12
green11 | 29 80 | red1
green13 | 30 79 | red15
green12 | 31 78 | red16
red9 | 32 77 | ^MSEL0
green10 | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
green9 | 36 73 | green16
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
R r R G r R r R V r R r R V r G V G c G G G r r V R g r r G R g R r V m
E o E N o E o E C o E o E C o N C N l N N N o o C E r s e N E r E e C a
S w S D w S w S C w S w S C w D C D k D D D w w C S e t d D S e S d C n
E 8 E 7 E 6 E I 5 E 4 E I 1 _ 2 _ 2 3 I E e 1 E e E 1 I u
R R R R O R R N C C O R n 1 R n R 4 O c
V V V V V V T K K V 1 V 1 V t
E E E E E E L L E 4 E 5 E r
D D D D D D K K D D D l
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: f:\traffic\traffic.rpt
traffic
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 4/22( 18%)
A2 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
A3 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
A6 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 1/22( 4%)
A7 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
A10 5/ 8( 62%) 3/ 8( 37%) 3/ 8( 37%) 0/2 0/2 5/22( 22%)
A14 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
A16 7/ 8( 87%) 4/ 8( 50%) 1/ 8( 12%) 0/2 0/2 13/22( 59%)
A17 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
A19 8/ 8(100%) 2/ 8( 25%) 6/ 8( 75%) 0/2 0/2 15/22( 68%)
A20 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
A21 6/ 8( 75%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 11/22( 50%)
A22 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 8/22( 36%)
A23 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 14/22( 63%)
A24 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 7/22( 31%)
A25 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
A26 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 13/22( 59%)
A27 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
A28 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 0/2 0/2 6/22( 27%)
A29 8/ 8(100%) 1/ 8( 12%) 7/ 8( 87%) 1/2 0/2 3/22( 13%)
A30 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 19/22( 86%)
A31 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 16/22( 72%)
A32 7/ 8( 87%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 15/22( 68%)
A33 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
A34 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 8/22( 36%)
A35 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 0/2 6/22( 27%)
A36 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 0/2 4/22( 18%)
B2 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 1/2 0/2 6/22( 27%)
B9 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 4/22( 18%)
B12 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 3/22( 13%)
B15 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 4/22( 18%)
B16 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 3/22( 13%)
D1 3/ 8( 37%) 3/ 8( 37%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
D3 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
D5 8/ 8(100%) 6/ 8( 75%) 2/ 8( 25%) 0/2 0/2 11/22( 50%)
D7 7/ 8( 87%) 4/ 8( 50%) 1/ 8( 12%) 0/2 0/2 15/22( 68%)
D8 8/ 8(100%) 2/ 8( 25%) 5/ 8( 62%) 0/2 0/2 8/22( 36%)
D9 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
D11 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 0/22( 0%)
D12 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
D13 4/ 8( 50%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
D15 7/ 8( 87%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
D16 3/ 8( 37%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 4/22( 18%)
D18 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 13/22( 59%)
D19 8/ 8(100%) 1/ 8( 12%) 6/ 8( 75%) 1/2 0/2 7/22( 31%)
D23 6/ 8( 75%) 2/ 8( 25%) 6/ 8( 75%) 0/2 0/2 9/22( 40%)
D28 8/ 8(100%) 1/ 8( 12%) 7/ 8( 87%) 0/2 0/2 11/22( 50%)
D30 8/ 8(100%) 1/ 8( 12%) 6/ 8( 75%) 0/2 0/2 10/22( 45%)
D32 2/ 8( 25%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 3/22( 13%)
D34 8/ 8(100%) 4/ 8( 50%) 6/ 8( 75%) 1/2 0/2 10/22( 45%)
D36 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
F6 8/ 8(100%) 4/ 8( 50%) 4/ 8( 50%) 0/2 0/2 6/22( 27%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 2/6 ( 33%)
Total I/O pins used: 56/96 ( 58%)
Total logic cells used: 289/1728 ( 16%)
Total embedded cells used: 0/96 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.40/4 ( 85%)
Total fan-in: 985/6912 ( 14%)
Total input pins required: 4
Total input I/O cell registers required: 0
Total output pins required: 54
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 289
Total flipflops required: 58
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 102/1728 ( 5%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 8 1 1 0 0 2 1 0 0 5 0 0 0 1 0 7 1 0 0 8 1 6 8 8 8 1 8 1 8 8 8 8 7 1 8 8 8 140/0
B: 0 8 0 0 0 0 0 0 8 0 0 2 0 0 8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 3 0 8 0 8 0 7 8 8 0 1 1 4 0 7 3 0 8 0 8 0 0 0 6 0 0 0 0 8 0 8 0 2 0 8 0 1 107/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8/0
Total: 11 9 9 0 8 10 8 8 16 5 1 3 4 1 15 18 1 8 0 16 1 6 8 14 8 1 8 1 16 8 16 8 9 1 16 8 9 289/0
Device-Specific Information: f:\traffic\traffic.rpt
traffic
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
125 - - - -- INPUT G ^ 0 0 0 0 clk1
55 - - - -- INPUT G ^ 0 0 0 0 clk2
72 - - - 03 INPUT ^ 0 0 0 2 manuctrl
64 - - - 10 INPUT ^ 0 0 0 12 rst
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\traffic\traffic.rpt
traffic
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
121 - - - 17 OUTPUT 0 1 0 0 a
117 - - - 08 OUTPUT 0 1 0 0 b
132 - - - 26 OUTPUT 0 1 0 0 c
119 - - - 13 OUTPUT 0 1 0 0 d
128 - - - 19 OUTPUT 0 1 0 0 dp
112 - - - 04 OUTPUT 0 1 0 0 e
131 - - - 23 OUTPUT 0 1 0 0 f
110 - - - 02 OUTPUT 0 1 0 0 g
88 - - D -- OUTPUT 0 1 0 0 green1
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