📄 digselector.rpt
字号:
Pin
18 -> * * * * * * * * * * * * * * | - - - * | <-- clk0
59 -> * * * * * * * * * * * * * * | - - - * | <-- clk1
27 -> * * * * * * * * * * * * * * | - - - * | <-- clk2
25 -> * - - - - - - - - - - - - - | - - - * | <-- digin10
22 -> - * - - - - - - - - - - - - | - - - * | <-- digin11
20 -> - - * - - - - - - - - - - - | - - - * | <-- digin12
37 -> - - - * - - - - - - - - - - | - - - * | <-- digin13
45 -> - - - - - - - - - - * - - - | - - - * | <-- digin20
46 -> - - - - - - - - - - - * - - | - - - * | <-- digin21
19 -> - - - - - - - - - - - - * - | - - - * | <-- digin22
23 -> - - - - - - - - - - - - - * | - - - * | <-- digin23
24 -> - - - - - - - - - - * - - - | - - - * | <-- digin30
33 -> - - - - - - - - - - - * - - | - - - * | <-- digin31
28 -> - - - - - - - - - - - - * - | - - - * | <-- digin32
29 -> - - - - - - - - - - - - - * | - - - * | <-- digin33
30 -> - - - - - - - - - - * - - - | - - - * | <-- digin40
17 -> - - - - - - - - - - - * - - | - - - * | <-- digin41
15 -> - - - - - - - - - - - - * - | - - - * | <-- digin42
14 -> - - - - - - - - - - - - - * | - - - * | <-- digin43
13 -> * - - - - - - - - - * - - - | - - - * | <-- digin50
12 -> - * - - - - - - - - - * - - | - - - * | <-- digin51
10 -> - - * - - - - - - - - - * - | - - - * | <-- digin52
9 -> - - - * - - - - - - - - - * | - - - * | <-- digin53
8 -> * - - - - - - - - - * - - - | - - - * | <-- digin60
7 -> - * - - - - - - - - - * - - | - - - * | <-- digin61
5 -> - - * - - - - - - - - - * - | - - - * | <-- digin62
4 -> - - - * - - - - - - - - - * | - - - * | <-- digin63
32 -> * * * * * * * * * * * * * * | - - - * | <-- digselect
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\traffic\digselector.rpt
digselector
** EQUATIONS **
clk0 : INPUT;
clk1 : INPUT;
clk2 : INPUT;
digin10 : INPUT;
digin11 : INPUT;
digin12 : INPUT;
digin13 : INPUT;
digin20 : INPUT;
digin21 : INPUT;
digin22 : INPUT;
digin23 : INPUT;
digin30 : INPUT;
digin31 : INPUT;
digin32 : INPUT;
digin33 : INPUT;
digin40 : INPUT;
digin41 : INPUT;
digin42 : INPUT;
digin43 : INPUT;
digin50 : INPUT;
digin51 : INPUT;
digin52 : INPUT;
digin53 : INPUT;
digin60 : INPUT;
digin61 : INPUT;
digin62 : INPUT;
digin63 : INPUT;
digselect : INPUT;
-- Node name is 'digout0'
-- Equation name is 'digout0', location is LC060, type is output.
digout0 = LCELL( _EQ001 $ VCC);
_EQ001 = !_LC050 & _X001 & _X002 & _X003;
_X001 = EXP(!clk0 & !clk1 & !clk2 & digin10 & digselect);
_X002 = EXP( clk0 & digin60 & !digselect);
_X003 = EXP(!clk0 & digin50 & !digselect);
-- Node name is 'digout1'
-- Equation name is 'digout1', location is LC061, type is output.
digout1 = LCELL( _EQ002 $ VCC);
_EQ002 = !_LC057 & _X004 & _X005 & _X006;
_X004 = EXP(!clk0 & !clk1 & !clk2 & digin11 & digselect);
_X005 = EXP( clk0 & digin61 & !digselect);
_X006 = EXP(!clk0 & digin51 & !digselect);
-- Node name is 'digout2'
-- Equation name is 'digout2', location is LC062, type is output.
digout2 = LCELL( _EQ003 $ VCC);
_EQ003 = !_LC049 & _X007 & _X008 & _X009;
_X007 = EXP(!clk0 & !clk1 & !clk2 & digin12 & digselect);
_X008 = EXP( clk0 & digin62 & !digselect);
_X009 = EXP(!clk0 & digin52 & !digselect);
-- Node name is 'digout3'
-- Equation name is 'digout3', location is LC064, type is output.
digout3 = LCELL( _EQ004 $ VCC);
_EQ004 = !_LC058 & _X010 & _X011 & _X012;
_X010 = EXP(!clk0 & !clk1 & !clk2 & digin13 & digselect);
_X011 = EXP( clk0 & digin63 & !digselect);
_X012 = EXP(!clk0 & digin53 & !digselect);
-- Node name is 'out0'
-- Equation name is 'out0', location is LC059, type is output.
out0 = LCELL( _EQ005 $ VCC);
_EQ005 = !clk0 & !clk1 & !clk2 & digselect
# clk1 & clk2 & digselect;
-- Node name is 'out1'
-- Equation name is 'out1', location is LC056, type is output.
out1 = LCELL( _EQ006 $ VCC);
_EQ006 = clk0 & !clk1 & !clk2 & digselect
# clk1 & clk2 & digselect;
-- Node name is 'out2'
-- Equation name is 'out2', location is LC054, type is output.
out2 = LCELL( _EQ007 $ !digselect);
_EQ007 = clk0 & clk1 & !clk2 & digselect
# !clk1 & digselect;
-- Node name is 'out3'
-- Equation name is 'out3', location is LC053, type is output.
out3 = LCELL( _EQ008 $ !digselect);
_EQ008 = !clk0 & clk1 & !clk2 & digselect
# !clk1 & digselect;
-- Node name is 'out4'
-- Equation name is 'out4', location is LC052, type is output.
out4 = LCELL( _EQ009 $ clk0);
_EQ009 = clk0 & clk1 & clk2 & digselect
# !clk0 & !clk2 & digselect;
-- Node name is 'out5'
-- Equation name is 'out5', location is LC051, type is output.
out5 = LCELL( _EQ010 $ !clk0);
_EQ010 = !clk0 & clk1 & clk2 & digselect
# clk0 & !clk2 & digselect;
-- Node name is '~195~1' from file "digselector.tdf" line 27, column 92
-- Equation name is '~195~1', location is LC050, type is buried.
-- synthesized logic cell
_LC050 = LCELL( _EQ011 $ GND);
_EQ011 = clk0 & clk1 & !clk2 & digin40 & digselect
# clk0 & !clk1 & clk2 & digin60 & digselect
# clk0 & !clk1 & !clk2 & digin20 & digselect
# !clk0 & clk1 & !clk2 & digin30 & digselect
# !clk0 & !clk1 & clk2 & digin50 & digselect;
-- Node name is '~197~1' from file "digselector.tdf" line 27, column 92
-- Equation name is '~197~1', location is LC057, type is buried.
-- synthesized logic cell
_LC057 = LCELL( _EQ012 $ GND);
_EQ012 = clk0 & clk1 & !clk2 & digin41 & digselect
# clk0 & !clk1 & clk2 & digin61 & digselect
# clk0 & !clk1 & !clk2 & digin21 & digselect
# !clk0 & clk1 & !clk2 & digin31 & digselect
# !clk0 & !clk1 & clk2 & digin51 & digselect;
-- Node name is '~199~1' from file "digselector.tdf" line 27, column 92
-- Equation name is '~199~1', location is LC049, type is buried.
-- synthesized logic cell
_LC049 = LCELL( _EQ013 $ GND);
_EQ013 = clk0 & clk1 & !clk2 & digin42 & digselect
# clk0 & !clk1 & clk2 & digin62 & digselect
# clk0 & !clk1 & !clk2 & digin22 & digselect
# !clk0 & clk1 & !clk2 & digin32 & digselect
# !clk0 & !clk1 & clk2 & digin52 & digselect;
-- Node name is '~201~1' from file "digselector.tdf" line 27, column 92
-- Equation name is '~201~1', location is LC058, type is buried.
-- synthesized logic cell
_LC058 = LCELL( _EQ014 $ GND);
_EQ014 = clk0 & clk1 & !clk2 & digin43 & digselect
# clk0 & !clk1 & clk2 & digin63 & digselect
# clk0 & !clk1 & !clk2 & digin23 & digselect
# !clk0 & clk1 & !clk2 & digin33 & digselect
# !clk0 & !clk1 & clk2 & digin53 & digselect;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\traffic\digselector.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 9,931K
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