📄 digselector.rpt
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Project Information e:\traffic\digselector.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 03/30/2009 19:18:18
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
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their respective licensors. No other licenses, including any licenses
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***** Project compilation was successful
Untitled
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
digselector
EPM7064LC68-7 28 10 0 14 12 21 %
User Pins: 28 10 0
Device-Specific Information: e:\traffic\digselector.rpt
digselector
***** Logic for device 'digselector' compiled without errors.
Device: EPM7064LC68-7
Device Options:
Turbo Bit = ON
Security Bit = OFF
MultiVolt I/O = OFF
d d d d d d d d d
i i i i i V i i i i
g g g g g C g g V g g
i i i i i C o o C o o
n n n G n n I G G G G G u u C u u
5 6 6 N 6 6 N N N N N N t t I t t
3 0 1 D 2 3 T D D D D D 3 2 O 1 0
-----------------------------------------------------_
/ 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 |
digin52 | 10 60 | out0
VCCIO | 11 59 | clk1
digin51 | 12 58 | GND
digin50 | 13 57 | out1
digin43 | 14 56 | out2
digin42 | 15 55 | out3
GND | 16 54 | out4
digin41 | 17 53 | VCCIO
clk0 | 18 EPM7064LC68-7 52 | out5
digin22 | 19 51 | RESERVED
digin12 | 20 50 | RESERVED
VCCIO | 21 49 | RESERVED
digin11 | 22 48 | GND
digin23 | 23 47 | RESERVED
digin30 | 24 46 | digin21
digin10 | 25 45 | digin20
GND | 26 44 | RESERVED
|_ 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 _|
------------------------------------------------------
c d d d V d d G V R d G R R R R V
l i i i C i i N C E i N E E E E C
k g g g C g g D C S g D S S S S C
2 i i i I s i I E i E E E E I
n n n O e n N R n R R R R O
3 3 4 l 3 T V 1 V V V V
2 3 0 e 1 E 3 E E E E
c D D D D D
t
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: e:\traffic\digselector.rpt
digselector
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 12/12(100%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 0/16( 0%) 12/12(100%) 0/16( 0%) 0/36( 0%)
C: LC33 - LC48 0/16( 0%) 3/12( 25%) 0/16( 0%) 0/36( 0%)
D: LC49 - LC64 14/16( 87%) 11/12( 91%) 16/16(100%) 32/36( 88%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 38/48 ( 79%)
Total logic cells used: 14/64 ( 21%)
Total shareable expanders used: 12/64 ( 18%)
Total Turbo logic cells used: 14/64 ( 21%)
Total shareable expanders not available (n/a): 4/64 ( 6%)
Average fan-in: 6.57
Total fan-in: 92
Total input pins required: 28
Total output pins required: 10
Total bidirectional pins required: 0
Total logic cells required: 14
Total flipflops required: 0
Total product terms required: 52
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 12
Synthesized logic cells: 4/ 64 ( 6%)
Device-Specific Information: e:\traffic\digselector.rpt
digselector
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
18 (1) (A) INPUT 0 0 0 0 0 10 4 clk0
59 (57) (D) INPUT 0 0 0 0 0 10 4 clk1
27 (24) (B) INPUT 0 0 0 0 0 10 4 clk2
25 (25) (B) INPUT 0 0 0 0 0 1 0 digin10
22 (29) (B) INPUT 0 0 0 0 0 1 0 digin11
20 (30) (B) INPUT 0 0 0 0 0 1 0 digin12
37 (35) (C) INPUT 0 0 0 0 0 1 0 digin13
45 (43) (C) INPUT 0 0 0 0 0 0 1 digin20
46 (44) (C) INPUT 0 0 0 0 0 0 1 digin21
19 (32) (B) INPUT 0 0 0 0 0 0 1 digin22
23 (28) (B) INPUT 0 0 0 0 0 0 1 digin23
24 (27) (B) INPUT 0 0 0 0 0 0 1 digin30
33 (17) (B) INPUT 0 0 0 0 0 0 1 digin31
28 (22) (B) INPUT 0 0 0 0 0 0 1 digin32
29 (21) (B) INPUT 0 0 0 0 0 0 1 digin33
30 (20) (B) INPUT 0 0 0 0 0 0 1 digin40
17 (3) (A) INPUT 0 0 0 0 0 0 1 digin41
15 (4) (A) INPUT 0 0 0 0 0 0 1 digin42
14 (5) (A) INPUT 0 0 0 0 0 0 1 digin43
13 (6) (A) INPUT 0 0 0 0 0 1 1 digin50
12 (8) (A) INPUT 0 0 0 0 0 1 1 digin51
10 (9) (A) INPUT 0 0 0 0 0 1 1 digin52
9 (11) (A) INPUT 0 0 0 0 0 1 1 digin53
8 (12) (A) INPUT 0 0 0 0 0 1 1 digin60
7 (13) (A) INPUT 0 0 0 0 0 1 1 digin61
5 (14) (A) INPUT 0 0 0 0 0 1 1 digin62
4 (16) (A) INPUT 0 0 0 0 0 1 1 digin63
32 (19) (B) INPUT 0 0 0 0 0 10 4 digselect
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\traffic\digselector.rpt
digselector
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
61 60 D OUTPUT t 3 0 0 7 1 0 0 digout0
62 61 D OUTPUT t 3 0 0 7 1 0 0 digout1
64 62 D OUTPUT t 3 0 0 7 1 0 0 digout2
65 64 D OUTPUT t 3 0 0 7 1 0 0 digout3
60 59 D OUTPUT t 0 0 0 4 0 0 0 out0
57 56 D OUTPUT t 0 0 0 4 0 0 0 out1
56 54 D OUTPUT t 0 0 0 4 0 0 0 out2
55 53 D OUTPUT t 0 0 0 4 0 0 0 out3
54 52 D OUTPUT t 0 0 0 4 0 0 0 out4
52 51 D OUTPUT t 0 0 0 4 0 0 0 out5
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\traffic\digselector.rpt
digselector
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 50 D SOFT s t 1 0 1 9 0 1 0 ~195~1
(59) 57 D SOFT s t 1 0 1 9 0 1 0 ~197~1
(51) 49 D SOFT s t 1 0 1 9 0 1 0 ~199~1
- 58 D SOFT s t 1 0 1 9 0 1 0 ~201~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\traffic\digselector.rpt
digselector
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+--------------------------- LC60 digout0
| +------------------------- LC61 digout1
| | +----------------------- LC62 digout2
| | | +--------------------- LC64 digout3
| | | | +------------------- LC59 out0
| | | | | +----------------- LC56 out1
| | | | | | +--------------- LC54 out2
| | | | | | | +------------- LC53 out3
| | | | | | | | +----------- LC52 out4
| | | | | | | | | +--------- LC51 out5
| | | | | | | | | | +------- LC50 ~195~1
| | | | | | | | | | | +----- LC57 ~197~1
| | | | | | | | | | | | +--- LC49 ~199~1
| | | | | | | | | | | | | +- LC58 ~201~1
| | | | | | | | | | | | | |
| | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
LC50 -> * - - - - - - - - - - - - - | - - - * | <-- ~195~1
LC57 -> - * - - - - - - - - - - - - | - - - * | <-- ~197~1
LC49 -> - - * - - - - - - - - - - - | - - - * | <-- ~199~1
LC58 -> - - - * - - - - - - - - - - | - - - * | <-- ~201~1
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