📄 disp.rpt
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-- Equation name is 'colred15', location is LC012, type is output.
colred15 = LCELL( _EQ019 $ !subcol1);
_EQ019 = maincol1 & subcol0 & !subcol1 & subtringle & !tringle
# subcol1 & subtringle & tringle
# !maincol1 & subcol1 & !tringle
# !maincol0 & !maincol1 & subcol1;
-- Node name is 'colred16'
-- Equation name is 'colred16', location is LC011, type is output.
colred16 = LCELL( _EQ020 $ !subcol1);
_EQ020 = maincol1 & subcol0 & !subcol1 & subtringle & !tringle
# subcol1 & subtringle & tringle
# !maincol1 & subcol1 & !tringle
# !maincol0 & !maincol1 & subcol1;
-- Node name is 'row1'
-- Equation name is 'row1', location is LC017, type is output.
row1 = LCELL( _EQ021 $ GND);
_EQ021 = !inputclk0 & !inputclk1 & !inputclk2 & subtringle & tringle
# !inputclk0 & !inputclk1 & !inputclk2 & !subcol0 & !subcol1
# !inputclk0 & !inputclk1 & !inputclk2 & !subcol1 & !subtringle
# !inputclk0 & !inputclk1 & !inputclk2 & !maincol1 & !tringle
# !inputclk0 & !inputclk1 & !inputclk2 & !maincol0 & !maincol1;
-- Node name is 'row2'
-- Equation name is 'row2', location is LC018, type is output.
row2 = LCELL( _EQ022 $ GND);
_EQ022 = inputclk0 & !inputclk1 & !inputclk2 & subtringle & tringle
# inputclk0 & !inputclk1 & !inputclk2 & !subcol0 & !subcol1
# inputclk0 & !inputclk1 & !inputclk2 & !subcol1 & !subtringle
# inputclk0 & !inputclk1 & !inputclk2 & !maincol1 & !tringle
# inputclk0 & !inputclk1 & !inputclk2 & !maincol0 & !maincol1;
-- Node name is 'row3'
-- Equation name is 'row3', location is LC019, type is output.
row3 = LCELL( _EQ023 $ GND);
_EQ023 = !inputclk0 & inputclk1 & !inputclk2 & subtringle & tringle
# !inputclk0 & inputclk1 & !inputclk2 & !subcol0 & !subcol1
# !inputclk0 & inputclk1 & !inputclk2 & !subcol1 & !subtringle
# !inputclk0 & inputclk1 & !inputclk2 & !maincol1 & !tringle
# !inputclk0 & inputclk1 & !inputclk2 & !maincol0 & !maincol1;
-- Node name is 'row4'
-- Equation name is 'row4', location is LC020, type is output.
row4 = LCELL( _EQ024 $ GND);
_EQ024 = inputclk0 & inputclk1 & !inputclk2 & subtringle & tringle
# inputclk0 & inputclk1 & !inputclk2 & !subcol0 & !subcol1
# inputclk0 & inputclk1 & !inputclk2 & !subcol1 & !subtringle
# inputclk0 & inputclk1 & !inputclk2 & !maincol1 & !tringle
# inputclk0 & inputclk1 & !inputclk2 & !maincol0 & !maincol1;
-- Node name is 'row5'
-- Equation name is 'row5', location is LC026, type is output.
row5 = LCELL( _EQ025 $ GND);
_EQ025 = !inputclk0 & !inputclk1 & inputclk2 & subtringle & tringle
# !inputclk0 & !inputclk1 & inputclk2 & !subcol0 & !subcol1
# !inputclk0 & !inputclk1 & inputclk2 & !subcol1 & !subtringle
# !inputclk0 & !inputclk1 & inputclk2 & !maincol1 & !tringle
# !inputclk0 & !inputclk1 & inputclk2 & !maincol0 & !maincol1;
-- Node name is 'row6'
-- Equation name is 'row6', location is LC025, type is output.
row6 = LCELL( _EQ026 $ GND);
_EQ026 = inputclk0 & !inputclk1 & inputclk2 & subtringle & tringle
# inputclk0 & !inputclk1 & inputclk2 & !subcol0 & !subcol1
# inputclk0 & !inputclk1 & inputclk2 & !subcol1 & !subtringle
# inputclk0 & !inputclk1 & inputclk2 & !maincol1 & !tringle
# inputclk0 & !inputclk1 & inputclk2 & !maincol0 & !maincol1;
-- Node name is 'row7'
-- Equation name is 'row7', location is LC024, type is output.
row7 = LCELL( _EQ027 $ GND);
_EQ027 = !inputclk0 & inputclk1 & inputclk2 & subtringle & tringle
# !inputclk0 & inputclk1 & inputclk2 & !subcol0 & !subcol1
# !inputclk0 & inputclk1 & inputclk2 & !subcol1 & !subtringle
# !inputclk0 & inputclk1 & inputclk2 & !maincol1 & !tringle
# !inputclk0 & inputclk1 & inputclk2 & !maincol0 & !maincol1;
-- Node name is 'row8'
-- Equation name is 'row8', location is LC013, type is output.
row8 = LCELL( _EQ028 $ GND);
_EQ028 = inputclk0 & inputclk1 & inputclk2 & subtringle & tringle
# inputclk0 & inputclk1 & inputclk2 & !subcol0 & !subcol1
# inputclk0 & inputclk1 & inputclk2 & !subcol1 & !subtringle
# inputclk0 & inputclk1 & inputclk2 & !maincol1 & !tringle
# inputclk0 & inputclk1 & inputclk2 & !maincol0 & !maincol1;
-- Node name is '~1922~1' from file "disp.tdf" line 147, column 19
-- Equation name is '~1922~1', location is LC023, type is buried.
-- synthesized logic cell
_LC023 = LCELL( _EQ029 $ GND);
_EQ029 = !inputclk0 & !inputclk1 & inputclk2 & maincol0 & !subtringle &
tringle
# clk & !inputclk0 & inputclk1 & !inputclk2 & !maincol0 &
!maincol1
# !inputclk0 & !inputclk1 & inputclk2 & maincol1 & !subcol0 &
!subcol1
# !inputclk0 & inputclk1 & !inputclk2 & !maincol0 & !maincol1 &
!tringle
# !inputclk0 & !inputclk1 & inputclk2 & maincol1 & !subtringle;
-- Node name is '~1922~2' from file "disp.tdf" line 147, column 19
-- Equation name is '~1922~2', location is LC022, type is buried.
-- synthesized logic cell
_LC022 = LCELL( _EQ030 $ GND);
_EQ030 = maincol0 & subcol1 & !subtringle & tringle
# maincol1 & subcol0 & subtringle & !tringle
# maincol1 & subcol1 & !tringle
# maincol1 & subcol1 & !subtringle;
-- Node name is '~1922~3' from file "disp.tdf" line 147, column 19
-- Equation name is '~1922~3', location is LC021, type is buried.
-- synthesized logic cell
_LC021 = LCELL( _EQ031 $ GND);
_EQ031 = clk & inputclk0 & inputclk1 & !inputclk2 & maincol1 & subcol1
# inputclk0 & inputclk1 & !inputclk2 & maincol0 & !maincol1 &
!tringle;
-- Node name is '~1923~1' from file "disp.tdf" line 147, column 19
-- Equation name is '~1923~1', location is LC005, type is buried.
-- synthesized logic cell
_LC005 = LCELL( _EQ032 $ GND);
_EQ032 = inputclk0 & !inputclk1 & !inputclk2 & !maincol1 & !tringle
# inputclk0 & !inputclk1 & !inputclk2 & !maincol0 & !maincol1;
-- Node name is '~1925~1' from file "disp.tdf" line 147, column 19
-- Equation name is '~1925~1', location is LC004, type is buried.
-- synthesized logic cell
_LC004 = LCELL( _EQ033 $ GND);
_EQ033 = inputclk0 & !inputclk1 & inputclk2 & !maincol1 & !tringle
# inputclk0 & !inputclk1 & inputclk2 & !maincol0 & !maincol1;
-- Node name is '~1926~1' from file "disp.tdf" line 147, column 19
-- Equation name is '~1926~1', location is LC029, type is buried.
-- synthesized logic cell
_LC029 = LCELL( _EQ034 $ GND);
_EQ034 = !inputclk0 & inputclk1 & !inputclk2 & maincol0 & !subtringle &
tringle
# clk & !inputclk0 & !inputclk1 & inputclk2 & !maincol0 &
!maincol1
# !inputclk0 & inputclk1 & !inputclk2 & maincol1 & !subcol0 &
!subcol1
# !inputclk0 & !inputclk1 & inputclk2 & !maincol0 & !maincol1 &
!tringle
# !inputclk0 & inputclk1 & !inputclk2 & maincol1 & !subtringle;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\traffic\disp.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:01
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 11,282K
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