disp.rpt

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** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'A':

                                     Logic cells placed in LAB 'A'
        +--------------------------- LC7 colred1
        | +------------------------- LC8 colred2
        | | +----------------------- LC15 colred8
        | | | +--------------------- LC16 colred9
        | | | | +------------------- LC1 colred10
        | | | | | +----------------- LC2 colred11
        | | | | | | +--------------- LC6 colred12
        | | | | | | | +------------- LC3 colred13
        | | | | | | | | +----------- LC14 colred14
        | | | | | | | | | +--------- LC12 colred15
        | | | | | | | | | | +------- LC11 colred16
        | | | | | | | | | | | +----- LC13 row8
        | | | | | | | | | | | | +--- LC5 ~1923~1
        | | | | | | | | | | | | | +- LC4 ~1925~1
        | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | |   that feed LAB 'A'
LC      | | | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'A':

Pin
7    -> - - - - - - - - - - - * * * | * * | <-- inputclk0
8    -> - - - - - - - - - - - * * * | * * | <-- inputclk1
27   -> - - - - - - - - - - - * * * | * * | <-- inputclk2
34   -> * * * * * * * * * * * * * * | * * | <-- maincol0
36   -> * * * * * * * * * * * * * * | * * | <-- maincol1
44   -> * * * * * * * * * * * * - - | * * | <-- subcol0
13   -> * * * * * * * * * * * * - - | * * | <-- subcol1
37   -> * * * * * * * * * * * * - - | * * | <-- subtringle
43   -> * * * * * * * * * * * * * * | * * | <-- tringle


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                               e:\traffic\disp.rpt
disp

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                                         Logic cells placed in LAB 'B'
        +------------------------------- LC32 colred3
        | +----------------------------- LC31 colred4
        | | +--------------------------- LC30 colred5
        | | | +------------------------- LC28 colred6
        | | | | +----------------------- LC27 colred7
        | | | | | +--------------------- LC17 row1
        | | | | | | +------------------- LC18 row2
        | | | | | | | +----------------- LC19 row3
        | | | | | | | | +--------------- LC20 row4
        | | | | | | | | | +------------- LC26 row5
        | | | | | | | | | | +----------- LC25 row6
        | | | | | | | | | | | +--------- LC24 row7
        | | | | | | | | | | | | +------- LC23 ~1922~1
        | | | | | | | | | | | | | +----- LC22 ~1922~2
        | | | | | | | | | | | | | | +--- LC21 ~1922~3
        | | | | | | | | | | | | | | | +- LC29 ~1926~1
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC23 -> * - - - - - - - - - - - - - - - | - * | <-- ~1922~1
LC22 -> * * - * * - - - - - - - - - - - | - * | <-- ~1922~2
LC21 -> * - - - * - - - - - - - - - - - | - * | <-- ~1922~3
LC29 -> - - - - * - - - - - - - - - - - | - * | <-- ~1926~1

Pin
14   -> * * * * * - - - - - - - * - * * | - * | <-- clk
7    -> * * * * * * * * * * * * * - * * | * * | <-- inputclk0
8    -> * * * * * * * * * * * * * - * * | * * | <-- inputclk1
27   -> * * - * * * * * * * * * * - * * | * * | <-- inputclk2
34   -> * * * * * * * * * * * * * * * * | * * | <-- maincol0
36   -> * * * * * * * * * * * * * * * * | * * | <-- maincol1
44   -> * * * * * * * * * * * * * * - * | * * | <-- subcol0
13   -> * * * * * * * * * * * * * * * * | * * | <-- subcol1
37   -> * * * * * * * * * * * * * * - * | * * | <-- subtringle
43   -> * * * * * * * * * * * * * * * * | * * | <-- tringle
LC5  -> - * - - - - - - - - - - - - - - | - * | <-- ~1923~1
LC4  -> - - - * - - - - - - - - - - - - | - * | <-- ~1925~1


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                               e:\traffic\disp.rpt
disp

** EQUATIONS **

clk      : INPUT;
inputclk0 : INPUT;
inputclk1 : INPUT;
inputclk2 : INPUT;
maincol0 : INPUT;
maincol1 : INPUT;
subcol0  : INPUT;
subcol1  : INPUT;
subtringle : INPUT;
tringle  : INPUT;

-- Node name is 'colred1' 
-- Equation name is 'colred1', location is LC007, type is output.
 colred1 = LCELL( _EQ001 $ !subcol1);
  _EQ001 =  maincol1 &  subcol0 & !subcol1 &  subtringle & !tringle
         #  subcol1 &  subtringle &  tringle
         # !maincol1 &  subcol1 & !tringle
         # !maincol0 & !maincol1 &  subcol1;

-- Node name is 'colred2' 
-- Equation name is 'colred2', location is LC008, type is output.
 colred2 = LCELL( _EQ002 $ !subcol1);
  _EQ002 =  maincol1 &  subcol0 & !subcol1 &  subtringle & !tringle
         #  subcol1 &  subtringle &  tringle
         # !maincol1 &  subcol1 & !tringle
         # !maincol0 & !maincol1 &  subcol1;

-- Node name is 'colred3' 
-- Equation name is 'colred3', location is LC032, type is output.
 colred3 = LCELL( _EQ003 $  _EQ004);
  _EQ003 =  clk &  inputclk0 &  inputclk1 & !inputclk2 & !_LC021 & !_LC022 & 
             !_LC023 &  maincol0 &  subcol0 &  subtringle
         #  clk &  inputclk0 &  inputclk1 & !inputclk2 & !_LC021 & !_LC022 & 
             !_LC023 &  maincol1 &  subcol0 &  subtringle
         # !inputclk0 & !inputclk1 &  inputclk2 & !_LC021 & !_LC022 & !_LC023 & 
              maincol0 & !subcol0 & !subcol1 &  tringle
         #  clk &  inputclk0 &  inputclk1 & !inputclk2 & !_LC021 & !_LC022 & 
             !_LC023 &  maincol0 &  subcol1;
  _EQ004 = !_LC021 & !_LC022 & !_LC023;

-- Node name is 'colred4' 
-- Equation name is 'colred4', location is LC031, type is output.
 colred4 = LCELL( _EQ005 $  _EQ006);
  _EQ005 =  clk &  inputclk0 & !inputclk1 &  inputclk2 & !_LC005 & !_LC022 & 
              maincol0 & !subcol0 & !subcol1 &  tringle
         #  clk &  inputclk0 & !inputclk1 &  inputclk2 & !_LC005 & !_LC022 & 
              maincol1 & !subcol0 & !subcol1
         #  inputclk0 & !inputclk1 &  inputclk2 & !_LC005 & !_LC022 & 
              maincol0 & !subcol0 & !subtringle &  tringle
         #  inputclk0 & !inputclk1 &  inputclk2 & !_LC005 & !_LC022 & 
              maincol1 & !subcol0 & !subtringle;
  _EQ006 = !_LC005 & !_LC022;

-- Node name is 'colred5' 
-- Equation name is 'colred5', location is LC030, type is output.
 colred5 = LCELL( _EQ007 $  GND);
  _EQ007 =  subtringle &  tringle &  _X001
         # !subcol1 & !subtringle &  _X002
         # !subcol0 & !subcol1
         # !maincol1 &  _X003;
  _X001  = EXP( clk &  inputclk0 & !inputclk1);
  _X002  = EXP( inputclk0 & !inputclk1);
  _X003  = EXP( maincol0 &  tringle);

-- Node name is 'colred6' 
-- Equation name is 'colred6', location is LC028, type is output.
 colred6 = LCELL( _EQ008 $  _EQ009);
  _EQ008 =  clk &  inputclk0 & !inputclk1 & !inputclk2 & !_LC004 & !_LC022 & 
              maincol0 & !subcol0 & !subcol1 &  tringle
         #  clk &  inputclk0 & !inputclk1 & !inputclk2 & !_LC004 & !_LC022 & 
              maincol1 & !subcol0 & !subcol1
         #  inputclk0 & !inputclk1 & !inputclk2 & !_LC004 & !_LC022 & 
              maincol0 & !subcol0 & !subtringle &  tringle
         #  inputclk0 & !inputclk1 & !inputclk2 & !_LC004 & !_LC022 & 
              maincol1 & !subcol0 & !subtringle;
  _EQ009 = !_LC004 & !_LC022;

-- Node name is 'colred7' 
-- Equation name is 'colred7', location is LC027, type is output.
 colred7 = LCELL( _EQ010 $  _EQ011);
  _EQ010 =  clk &  inputclk0 &  inputclk1 & !inputclk2 & !_LC021 & !_LC022 & 
             !_LC029 &  maincol0 &  subcol0 &  subtringle
         #  clk &  inputclk0 &  inputclk1 & !inputclk2 & !_LC021 & !_LC022 & 
             !_LC029 &  maincol1 &  subcol0 &  subtringle
         # !inputclk0 &  inputclk1 & !inputclk2 & !_LC021 & !_LC022 & !_LC029 & 
              maincol0 & !subcol0 & !subcol1 &  tringle
         #  clk &  inputclk0 &  inputclk1 & !inputclk2 & !_LC021 & !_LC022 & 
             !_LC029 &  maincol0 &  subcol1;
  _EQ011 = !_LC021 & !_LC022 & !_LC029;

-- Node name is 'colred8' 
-- Equation name is 'colred8', location is LC015, type is output.
 colred8 = LCELL( _EQ012 $ !subcol1);
  _EQ012 =  maincol1 &  subcol0 & !subcol1 &  subtringle & !tringle
         #  subcol1 &  subtringle &  tringle
         # !maincol1 &  subcol1 & !tringle
         # !maincol0 & !maincol1 &  subcol1;

-- Node name is 'colred9' 
-- Equation name is 'colred9', location is LC016, type is output.
 colred9 = LCELL( _EQ013 $ !subcol1);
  _EQ013 =  maincol1 &  subcol0 & !subcol1 &  subtringle & !tringle
         #  subcol1 &  subtringle &  tringle
         # !maincol1 &  subcol1 & !tringle
         # !maincol0 & !maincol1 &  subcol1;

-- Node name is 'colred10' 
-- Equation name is 'colred10', location is LC001, type is output.
 colred10 = LCELL( _EQ014 $ !subcol1);
  _EQ014 =  maincol1 &  subcol0 & !subcol1 &  subtringle & !tringle
         #  subcol1 &  subtringle &  tringle
         # !maincol1 &  subcol1 & !tringle
         # !maincol0 & !maincol1 &  subcol1;

-- Node name is 'colred11' 
-- Equation name is 'colred11', location is LC002, type is output.
 colred11 = LCELL( _EQ015 $ !subcol1);
  _EQ015 =  maincol1 &  subcol0 & !subcol1 &  subtringle & !tringle
         #  subcol1 &  subtringle &  tringle
         # !maincol1 &  subcol1 & !tringle
         # !maincol0 & !maincol1 &  subcol1;

-- Node name is 'colred12' 
-- Equation name is 'colred12', location is LC006, type is output.
 colred12 = LCELL( _EQ016 $ !subcol1);
  _EQ016 =  maincol1 &  subcol0 & !subcol1 &  subtringle & !tringle
         #  subcol1 &  subtringle &  tringle
         # !maincol1 &  subcol1 & !tringle
         # !maincol0 & !maincol1 &  subcol1;

-- Node name is 'colred13' 
-- Equation name is 'colred13', location is LC003, type is output.
 colred13 = LCELL( _EQ017 $ !subcol1);
  _EQ017 =  maincol1 &  subcol0 & !subcol1 &  subtringle & !tringle
         #  subcol1 &  subtringle &  tringle
         # !maincol1 &  subcol1 & !tringle
         # !maincol0 & !maincol1 &  subcol1;

-- Node name is 'colred14' 
-- Equation name is 'colred14', location is LC014, type is output.
 colred14 = LCELL( _EQ018 $ !subcol1);
  _EQ018 =  maincol1 &  subcol0 & !subcol1 &  subtringle & !tringle
         #  subcol1 &  subtringle &  tringle
         # !maincol1 &  subcol1 & !tringle
         # !maincol0 & !maincol1 &  subcol1;

-- Node name is 'colred15'