📄 disp.rpt
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Project Information e:\traffic\disp.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 03/30/2009 19:35:11
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
Untitled
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
disp EPM7032LC44-6 10 24 0 30 3 93 %
User Pins: 10 24 0
Device-Specific Information: e:\traffic\disp.rpt
disp
***** Logic for device 'disp' compiled without errors.
Device: EPM7032LC44-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
Device-Specific Information: e:\traffic\disp.rpt
disp
** ERROR SUMMARY **
Info: Chip 'disp' in device 'EPM7032LC44-6' has less than 10% of logic cells available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
Info: Chip 'disp' in device 'EPM7032LC44-6' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
c c c
o o o s t
l l l u r
r r r b i
e e e c n r r
d d d V G G o g G o o
1 1 1 C N N l l N w w
3 1 0 C D D 0 e D 1 2
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
inputclk0 | 7 39 | row3
inputclk1 | 8 38 | row4
colred12 | 9 37 | subtringle
GND | 10 36 | maincol1
colred1 | 11 35 | VCC
colred2 | 12 EPM7032LC44-6 34 | maincol0
subcol1 | 13 33 | row7
clk | 14 32 | row6
VCC | 15 31 | row5
colred16 | 16 30 | GND
colred15 | 17 29 | colred7
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
r c c c G V c c c i c
o o o o N C o o o n o
w l l l D C l l l p l
8 r r r r r r u r
e e e e e e t e
d d d d d d c d
1 8 9 3 4 5 l 6
4 k
2
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: e:\traffic\disp.rpt
disp
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 14/16( 87%) 16/16(100%) 12/16( 75%) 9/36( 25%)
B: LC17 - LC32 16/16(100%) 16/16(100%) 16/16(100%) 16/36( 44%)
Total dedicated input pins used: 2/4 ( 50%)
Total I/O pins used: 32/32 (100%)
Total logic cells used: 30/32 ( 93%)
Total shareable expanders used: 3/32 ( 9%)
Total Turbo logic cells used: 30/32 ( 93%)
Total shareable expanders not available (n/a): 25/32 ( 78%)
Average fan-in: 8.10
Total fan-in: 243
Total input pins required: 10
Total output pins required: 24
Total bidirectional pins required: 0
Total logic cells required: 30
Total flipflops required: 0
Total product terms required: 142
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 3
Synthesized logic cells: 6/ 32 ( 18%)
Device-Specific Information: e:\traffic\disp.rpt
disp
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
14 (10) (A) INPUT 0 0 0 0 0 5 3 clk
7 (4) (A) INPUT 0 0 0 0 0 13 5 inputclk0
8 (5) (A) INPUT 0 0 0 0 0 13 5 inputclk1
27 (29) (B) INPUT 0 0 0 0 0 12 5 inputclk2
34 (23) (B) INPUT 0 0 0 0 0 24 6 maincol0
36 (22) (B) INPUT 0 0 0 0 0 24 6 maincol1
44 - - INPUT 0 0 0 0 0 24 3 subcol0
13 (9) (A) INPUT 0 0 0 0 0 24 4 subcol1
37 (21) (B) INPUT 0 0 0 0 0 24 3 subtringle
43 - - INPUT 0 0 0 0 0 24 6 tringle
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\traffic\disp.rpt
disp
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
11 7 A OUTPUT t 1 0 1 6 0 0 0 colred1
12 8 A OUTPUT t 1 0 1 6 0 0 0 colred2
24 32 B OUTPUT t 1 0 1 10 3 0 0 colred3
25 31 B OUTPUT t 1 0 1 10 2 0 0 colred4
26 30 B OUTPUT t 3 0 0 9 0 0 0 colred5
28 28 B OUTPUT t 1 0 1 10 2 0 0 colred6
29 27 B OUTPUT t 1 0 1 10 3 0 0 colred7
20 15 A OUTPUT t 1 0 1 6 0 0 0 colred8
21 16 A OUTPUT t 1 0 1 6 0 0 0 colred9
4 1 A OUTPUT t 1 0 1 6 0 0 0 colred10
5 2 A OUTPUT t 1 0 1 6 0 0 0 colred11
9 6 A OUTPUT t 1 0 1 6 0 0 0 colred12
6 3 A OUTPUT t 1 0 1 6 0 0 0 colred13
19 14 A OUTPUT t 1 0 1 6 0 0 0 colred14
17 12 A OUTPUT t 1 0 1 6 0 0 0 colred15
16 11 A OUTPUT t 1 0 1 6 0 0 0 colred16
41 17 B OUTPUT t 1 0 1 9 0 0 0 row1
40 18 B OUTPUT t 1 0 1 9 0 0 0 row2
39 19 B OUTPUT t 1 0 1 9 0 0 0 row3
38 20 B OUTPUT t 1 0 1 9 0 0 0 row4
31 26 B OUTPUT t 1 0 1 9 0 0 0 row5
32 25 B OUTPUT t 1 0 1 9 0 0 0 row6
33 24 B OUTPUT t 1 0 1 9 0 0 0 row7
18 13 A OUTPUT t 1 0 1 9 0 0 0 row8
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\traffic\disp.rpt
disp
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(34) 23 B SOFT s t 1 0 1 10 0 1 0 ~1922~1
(36) 22 B SOFT s t 0 0 0 6 0 4 0 ~1922~2
(37) 21 B SOFT s t 0 0 0 8 0 2 0 ~1922~3
(8) 5 A SOFT s t 0 0 0 6 0 1 0 ~1923~1
(7) 4 A SOFT s t 0 0 0 6 0 1 0 ~1925~1
(27) 29 B SOFT s t 1 0 1 10 0 1 0 ~1926~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\traffic\disp.rpt
disp
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