📄 hourcount.rpt
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| | | | | +----------- LC22 count5
| | | | | | +--------- LC17 hour0
| | | | | | | +------- LC18 hour1
| | | | | | | | +----- LC21 hour2
| | | | | | | | | +--- LC20 hour3
| | | | | | | | | | +- LC19 hour4
| | | | | | | | | | |
| | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC24 -> * * * * * * * * * * * | - * | <-- count0
LC26 -> - * * * * * * * * * * | - * | <-- count1
LC27 -> - - * * * * * * * * * | - * | <-- count2
LC25 -> - - * * * * * * * * * | - * | <-- count3
LC23 -> - - * * * * * * * * * | - * | <-- count4
LC22 -> - - * * * * * * * * * | - * | <-- count5
LC17 -> - - - - - - * * * * * | - * | <-- hour0
LC18 -> - - - - - - - * * * * | - * | <-- hour1
LC21 -> - - - - - - - - * * * | - * | <-- hour2
LC20 -> - - - - - - - - - * * | - * | <-- hour3
LC19 -> - - - - - - - - - * * | - * | <-- hour4
Pin
43 -> - - - - - - - - - - - | - - | <-- clk
4 -> - - - - - - * * * * * | - * | <-- manu
5 -> * * * * * * * * * * * | - * | <-- rst
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\traffic\hourcount.rpt
hourcount
** EQUATIONS **
clk : INPUT;
manu : INPUT;
rst : INPUT;
-- Node name is 'count0' from file "hourcount.tdf" line 9, column 7
-- Equation name is 'count0', location is LC024, type is buried.
count0 = DFFE( _EQ001 $ !rst, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = count0 & !rst;
-- Node name is 'count1' from file "hourcount.tdf" line 9, column 7
-- Equation name is 'count1', location is LC026, type is buried.
count1 = DFFE( _EQ002 $ !rst, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = count0 & count1 & !rst
# !count0 & !count1 & !rst;
-- Node name is 'count2' from file "hourcount.tdf" line 9, column 7
-- Equation name is 'count2', location is LC027, type is buried.
count2 = DFFE( _EQ003 $ !rst, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = count0 & count1 & !count2 & count3 & count4 & count5 & !rst
# count0 & count1 & count2 & !rst
# !count1 & !count2 & !rst
# !count0 & !count2 & !rst;
-- Node name is 'count3' from file "hourcount.tdf" line 9, column 7
-- Equation name is 'count3', location is LC025, type is buried.
count3 = TFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = count0 & count1 & !count2 & count3 & count4 & count5
# count0 & count1 & count2 & !count3 & !rst
# count0 & count1 & count2 & count3
# count3 & rst;
-- Node name is 'count4' from file "hourcount.tdf" line 9, column 7
-- Equation name is 'count4', location is LC023, type is buried.
count4 = TFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = count0 & count1 & !count2 & count3 & count4 & count5
# count0 & count1 & count2 & count3 & !count4 & !rst
# count0 & count1 & count2 & count3 & count4
# count4 & rst;
-- Node name is 'count5' from file "hourcount.tdf" line 9, column 7
-- Equation name is 'count5', location is LC022, type is buried.
count5 = TFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = count0 & count1 & count2 & count3 & count4 & !count5 & !rst
# count0 & count1 & count3 & count4 & count5
# count5 & rst;
-- Node name is 'hour0' = 'hourcount0' from file "hourcount.tdf" line 10, column 11
-- Equation name is 'hour0', location is LC017, type is output.
hour0 = DFFE( _EQ007 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = count0 & count1 & !count2 & count3 & count4 & count5 & !hour0 &
!rst
# !hour0 & manu;
-- Node name is 'hour1' = 'hourcount1' from file "hourcount.tdf" line 10, column 11
-- Equation name is 'hour1', location is LC018, type is output.
hour1 = DFFE( _EQ008 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = count0 & count1 & !count2 & count3 & count4 & count5 & hour0 &
!hour1 & !rst
# count0 & count1 & !count2 & count3 & count4 & count5 & !hour0 &
hour1 & !rst
# hour0 & !hour1 & manu
# !hour0 & hour1 & manu;
-- Node name is 'hour2' = 'hourcount2' from file "hourcount.tdf" line 10, column 11
-- Equation name is 'hour2', location is LC021, type is output.
hour2 = DFFE( _EQ009 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = count0 & count1 & !count2 & count3 & count4 & count5 & hour0 &
hour1 & !hour2 & !rst
# count0 & count1 & !count2 & count3 & count4 & count5 & hour2 &
!rst & _X001
# hour0 & hour1 & !hour2 & manu
# hour2 & manu & _X001;
_X001 = EXP( hour0 & hour1);
-- Node name is 'hour3' = 'hourcount3' from file "hourcount.tdf" line 10, column 11
-- Equation name is 'hour3', location is LC020, type is output.
hour3 = DFFE( _EQ010 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = count0 & count1 & !count2 & count3 & count4 & count5 & hour0 &
hour1 & hour2 & !hour3 & !hour4 & !rst
# count0 & count1 & !count2 & count3 & count4 & count5 & hour3 &
!rst & _X002
# hour0 & hour1 & hour2 & !hour3 & !hour4 & manu
# hour3 & manu & _X002;
_X002 = EXP( hour0 & hour1 & hour2);
-- Node name is 'hour4' = 'hourcount4' from file "hourcount.tdf" line 10, column 11
-- Equation name is 'hour4', location is LC019, type is output.
hour4 = DFFE( _EQ011 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = count0 & count1 & !count2 & count3 & count4 & count5 & hour0 &
hour1 & hour2 & hour3 & !hour4 & !rst
# count0 & count1 & !count2 & count3 & count4 & count5 & hour4 &
!rst & _X002
# hour0 & hour1 & hour2 & hour3 & !hour4 & manu
# hour4 & manu & _X002;
_X002 = EXP( hour0 & hour1 & hour2);
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\traffic\hourcount.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:00
Memory Allocated
-----------------
Peak memory allocated during compilation = 5,405K
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