main.rpt

veriloghdl 交通灯veriloghdl 交通灯veriloghdl 交通灯veriloghdl 交通灯veriloghdl 交通灯veriloghdl 交通灯veriloghdl 交通灯

        | | | | | | | | | | | +--- LC23 tringle
        | | | | | | | | | | | | +- LC29 :66
        | | | | | | | | | | | | | 
        | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC29 -> - - * * - - - * * * * * - | - * | <-- :66

Pin
14   -> - * * * - - - * * * * * * | - * | <-- hour0
13   -> - * * * - - - * * * * * * | - * | <-- hour1
12   -> - * * * - - - * * * * * * | - * | <-- hour2
11   -> - * * * - - - * * * * * * | - * | <-- hour3
9    -> - * * * - - - * * * * * * | - * | <-- hour4
8    -> - * * * - - - * * * * * - | - * | <-- incount0
4    -> - * * * - - - * * * * * - | - * | <-- incount1
7    -> - * * * - - - * * * * * - | - * | <-- incount2
6    -> * * * * - - - * * * * * - | - * | <-- incount3
5    -> * * * * - - - * * * * * - | - * | <-- incount4


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                               e:\traffic\main.rpt
main

** EQUATIONS **

hour0    : INPUT;
hour1    : INPUT;
hour2    : INPUT;
hour3    : INPUT;
hour4    : INPUT;
incount0 : INPUT;
incount1 : INPUT;
incount2 : INPUT;
incount3 : INPUT;
incount4 : INPUT;

-- Node name is 'digselect' 
-- Equation name is 'digselect', location is LC022, type is output.
 digselect = LCELL( _EQ001 $ !incount4);
  _EQ001 = !incount3 &  incount4;

-- Node name is 'maincol0' 
-- Equation name is 'maincol0', location is LC028, type is output.
 maincol0 = LCELL( _EQ002 $  GND);
  _EQ002 = !hour0 & !hour1 & !hour2 & !hour3 & !hour4 &  _X001
         #  hour0 &  hour1 &  hour2 &  hour4 &  _X001
         #  incount0 &  incount1 & !incount2 &  incount3 & !incount4
         # !incount0 & !incount1 &  incount2 &  incount3 & !incount4
         #  hour3 &  hour4 &  _X001;
  _X001  = EXP( incount3 &  incount4);

-- Node name is 'maincol1' 
-- Equation name is 'maincol1', location is LC026, type is output.
 maincol1 = LCELL( _EQ003 $  GND);
  _EQ003 = !incount0 &  incount1 &  incount2 &  incount3 & !incount4 & 
              _LC029 &  _X002
         #  incount0 &  incount2 &  incount3 & !incount4 &  _LC029 &  _X002
         # !incount3 &  incount4 &  _LC029 &  _X002;
  _X002  = EXP(!hour0 & !hour1 & !hour2 & !hour3 & !hour4);

-- Node name is 'out10' 
-- Equation name is 'out10', location is LC027, type is output.
 out10   = LCELL( _EQ004 $  GND);
  _EQ004 =  hour4 &  incount0 & !incount1 &  incount2 &  incount3 & !incount4 & 
              _LC029
         #  incount0 & !incount1 &  incount2 &  incount3 & !incount4 & 
              _LC029 &  _X003
         #  hour4 & !incount0 & !incount1 & !incount2 & !incount3 & !incount4 & 
              _LC029
         # !incount0 & !incount1 & !incount2 & !incount3 & !incount4 & 
              _LC029 &  _X003;
  _X003  = EXP(!hour0 & !hour1 & !hour2 & !hour3);

-- Node name is 'out11' 
-- Equation name is 'out11', location is LC025, type is output.
 out11   = LCELL( GND $  GND);

-- Node name is 'out12' 
-- Equation name is 'out12', location is LC024, type is output.
 out12   = LCELL( GND $  GND);

-- Node name is 'out13' 
-- Equation name is 'out13', location is LC018, type is output.
 out13   = LCELL( GND $  GND);

-- Node name is 'out20' 
-- Equation name is 'out20', location is LC017, type is output.
 out20   = LCELL( _EQ005 $  GND);
  _EQ005 = !incount0 &  incount1 &  incount2 &  incount3 & !incount4 & 
              _LC029 &  _X002
         #  incount0 & !incount2 &  incount3 & !incount4 &  _LC029 &  _X002
         #  incount0 & !incount3 & !incount4 &  _LC029 &  _X002
         # !incount0 & !incount3 &  incount4 &  _LC029 &  _X002;
  _X002  = EXP(!hour0 & !hour1 & !hour2 & !hour3 & !hour4);

-- Node name is 'out21' 
-- Equation name is 'out21', location is LC019, type is output.
 out21   = LCELL( _EQ006 $  GND);
  _EQ006 = !incount0 & !incount1 & !incount2 &  incount3 & !incount4 & 
              _LC029 &  _X002
         #  incount0 &  incount1 & !incount3 & !incount4 &  _LC029 &  _X002
         # !incount0 & !incount1 &  incount2 & !incount3 &  _LC029 &  _X002
         # !incount1 & !incount3 &  incount4 &  _LC029 &  _X002;
  _X002  = EXP(!hour0 & !hour1 & !hour2 & !hour3 & !hour4);

-- Node name is 'out22' 
-- Equation name is 'out22', location is LC020, type is output.
 out22   = LCELL( _EQ007 $  GND);
  _EQ007 =  incount0 &  incount1 & !incount2 & !incount3 &  _LC029 &  _X002
         # !incount0 &  incount2 & !incount3 & !incount4 &  _LC029 &  _X002
         # !incount1 &  incount2 & !incount3 & !incount4 &  _LC029 &  _X002
         # !incount2 & !incount3 &  incount4 &  _LC029 &  _X002;
  _X002  = EXP(!hour0 & !hour1 & !hour2 & !hour3 & !hour4);

-- Node name is 'out23' 
-- Equation name is 'out23', location is LC021, type is output.
 out23   = LCELL( _EQ008 $  GND);
  _EQ008 =  incount0 & !incount1 & !incount2 & !incount3 & !incount4 & 
              _LC029 &  _X002
         # !incount0 &  incount1 & !incount2 & !incount3 & !incount4 & 
              _LC029 &  _X002
         #  incount1 &  incount2 &  incount3 & !incount4 &  _LC029 &  _X002;
  _X002  = EXP(!hour0 & !hour1 & !hour2 & !hour3 & !hour4);

-- Node name is 'tringle' 
-- Equation name is 'tringle', location is LC023, type is output.
 tringle = LCELL( _EQ009 $  VCC);
  _EQ009 =  incount0 &  incount1 &  _LC029 &  _X002
         #  incount2 &  _LC029 &  _X002
         # !incount3 &  _LC029 &  _X002
         #  incount3 &  incount4;
  _X002  = EXP(!hour0 & !hour1 & !hour2 & !hour3 & !hour4);

-- Node name is ':66' from file "main.tdf" line 12, column 39
-- Equation name is '_LC029', type is buried 
_LC029   = LCELL( _EQ010 $  VCC);
  _EQ010 =  hour0 &  hour1 &  hour2 &  hour4
         #  hour3 &  hour4;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                        e:\traffic\main.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:00


Memory Allocated
-----------------

Peak memory allocated during compilation  = 11,762K