📄 main.rpt
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Project Information e:\traffic\main.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 03/30/2009 19:56:27
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
Untitled
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
main EPM7032LC44-6 10 12 0 13 3 40 %
User Pins: 10 12 0
Project Information e:\traffic\main.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Primitive 'out13' is stuck at GND
Warning: Primitive 'out12' is stuck at GND
Warning: Primitive 'out11' is stuck at GND
Device-Specific Information: e:\traffic\main.rpt
main
***** Logic for device 'main' compiled without errors.
Device: EPM7032LC44-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
i i i
n n n
c c c
o o o o o
u u u u u
n n n V G G G G G t t
t t t C N N N N N 2 1
3 4 1 C D D D D D 0 3
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
incount2 | 7 39 | out21
incount0 | 8 38 | out22
hour4 | 9 37 | out23
GND | 10 36 | digselect
hour3 | 11 35 | VCC
hour2 | 12 EPM7032LC44-6 34 | tringle
hour1 | 13 33 | out12
hour0 | 14 32 | out11
VCC | 15 31 | maincol1
RESERVED | 16 30 | GND
RESERVED | 17 29 | out10
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
R R R R G V R R R R m
E E E E N C E E E E a
S S S S D C S S S S i
E E E E E E E E n
R R R R R R R R c
V V V V V V V V o
E E E E E E E E l
D D D D D D D D 0
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: e:\traffic\main.rpt
main
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 10/16( 62%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 13/16( 81%) 12/16( 75%) 4/16( 25%) 11/36( 30%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 22/32 ( 68%)
Total logic cells used: 13/32 ( 40%)
Total shareable expanders used: 3/32 ( 9%)
Total Turbo logic cells used: 13/32 ( 40%)
Total shareable expanders not available (n/a): 1/32 ( 3%)
Average fan-in: 7.23
Total fan-in: 94
Total input pins required: 10
Total output pins required: 12
Total bidirectional pins required: 0
Total logic cells required: 13
Total flipflops required: 0
Total product terms required: 41
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 3
Synthesized logic cells: 0/ 32 ( 0%)
Device-Specific Information: e:\traffic\main.rpt
main
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
14 (10) (A) INPUT 0 0 0 0 0 8 1 hour0
13 (9) (A) INPUT 0 0 0 0 0 8 1 hour1
12 (8) (A) INPUT 0 0 0 0 0 8 1 hour2
11 (7) (A) INPUT 0 0 0 0 0 8 1 hour3
9 (6) (A) INPUT 0 0 0 0 0 8 1 hour4
8 (5) (A) INPUT 0 0 0 0 0 8 0 incount0
4 (1) (A) INPUT 0 0 0 0 0 8 0 incount1
7 (4) (A) INPUT 0 0 0 0 0 8 0 incount2
6 (3) (A) INPUT 0 0 0 0 0 9 0 incount3
5 (2) (A) INPUT 0 0 0 0 0 9 0 incount4
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\traffic\main.rpt
main
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
36 22 B OUTPUT t 0 0 0 2 0 0 0 digselect
28 28 B OUTPUT t 2 0 1 10 0 0 0 maincol0
31 26 B OUTPUT t 1 1 0 10 1 0 0 maincol1
29 27 B OUTPUT t 1 0 0 10 1 0 0 out10
32 25 B OUTPUT t 0 0 0 0 0 0 0 out11
33 24 B OUTPUT t 0 0 0 0 0 0 0 out12
40 18 B OUTPUT t 0 0 0 0 0 0 0 out13
41 17 B OUTPUT t 1 1 0 10 1 0 0 out20
39 19 B OUTPUT t 1 1 0 10 1 0 0 out21
38 20 B OUTPUT t 1 1 0 10 1 0 0 out22
37 21 B OUTPUT t 1 1 0 10 1 0 0 out23
34 23 B OUTPUT t 1 1 0 10 1 0 0 tringle
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\traffic\main.rpt
main
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(27) 29 B SOFT t 0 0 0 5 0 7 0 :66
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\traffic\main.rpt
main
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------- LC22 digselect
| +----------------------- LC28 maincol0
| | +--------------------- LC26 maincol1
| | | +------------------- LC27 out10
| | | | +----------------- LC25 out11
| | | | | +--------------- LC24 out12
| | | | | | +------------- LC18 out13
| | | | | | | +----------- LC17 out20
| | | | | | | | +--------- LC19 out21
| | | | | | | | | +------- LC20 out22
| | | | | | | | | | +----- LC21 out23
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