subroad.rpt

veriloghdl 交通灯veriloghdl 交通灯veriloghdl 交通灯veriloghdl 交通灯veriloghdl 交通灯veriloghdl 交通灯veriloghdl 交通灯

Pin
4    -> * * * * - - - * * * * * * | - * | <-- hour0
14   -> * * * * - - - * * * * * * | - * | <-- hour1
13   -> * * * * - - - * * * * * * | - * | <-- hour2
12   -> * * * * - - - * * * * * * | - * | <-- hour3
11   -> * * * * - - - * * * * * * | - * | <-- hour4
9    -> - * * * - - - * * * * * - | - * | <-- incount0
8    -> * * * * - - - * * * * * - | - * | <-- incount1
7    -> * * * * - - - * * * * * - | - * | <-- incount2
6    -> * * * * - - - * * * * * - | - * | <-- incount3
5    -> * * * * - - - * * * * * - | - * | <-- incount4


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                            e:\traffic\subroad.rpt
subroad

** EQUATIONS **

hour0    : INPUT;
hour1    : INPUT;
hour2    : INPUT;
hour3    : INPUT;
hour4    : INPUT;
incount0 : INPUT;
incount1 : INPUT;
incount2 : INPUT;
incount3 : INPUT;
incount4 : INPUT;

-- Node name is 'subcol0' 
-- Equation name is 'subcol0', location is LC027, type is output.
 subcol0 = LCELL( _EQ001 $ !_LC025);
  _EQ001 = !hour0 & !hour1 & !hour2 & !hour3 & !hour4 & !incount3 &  _LC025
         # !hour0 & !hour1 & !hour2 & !hour3 & !hour4 & !incount4 &  _LC025
         #  incount1 &  incount2 & !incount3 &  incount4 &  _LC025
         #  incount3 &  incount4 & !_LC025;

-- Node name is 'subcol1' 
-- Equation name is 'subcol1', location is LC029, type is output.
 subcol1 = LCELL( _EQ002 $  _LC025);
  _EQ002 = !hour0 & !hour1 & !hour2 & !hour3 & !hour4 &  _LC025
         #  incount0 &  incount2 &  incount3 &  _LC025
         #  incount1 &  incount2 &  incount3 &  _LC025
         #  incount4 &  _LC025;

-- Node name is 'subdigselect' 
-- Equation name is 'subdigselect', location is LC028, type is output.
 subdigselect = LCELL( _EQ003 $  VCC);
  _EQ003 =  incount0 &  incount1 & !incount2 &  incount3 &  _LC025 &  _X001
         # !incount0 & !incount1 &  incount2 &  incount3 &  _LC025 &  _X001
         #  incount1 &  incount2 &  incount4 &  _LC025 &  _X001
         #  incount3 &  incount4;
  _X001  = EXP(!hour0 & !hour1 & !hour2 & !hour3 & !hour4);

-- Node name is 'subout10' 
-- Equation name is 'subout10', location is LC026, type is output.
 subout10 = LCELL( _EQ004 $  GND);
  _EQ004 =  hour4 & !incount0 &  incount1 & !incount2 & !incount3 & !incount4 & 
              _LC025
         # !incount0 &  incount1 & !incount2 & !incount3 & !incount4 & 
              _LC025 &  _X002
         #  hour4 & !incount1 & !incount2 & !incount3 & !incount4 &  _LC025
         # !incount1 & !incount2 & !incount3 & !incount4 &  _LC025 &  _X002;
  _X002  = EXP(!hour0 & !hour1 & !hour2 & !hour3);

-- Node name is 'subout11' 
-- Equation name is 'subout11', location is LC024, type is output.
 subout11 = LCELL( GND $  GND);

-- Node name is 'subout12' 
-- Equation name is 'subout12', location is LC017, type is output.
 subout12 = LCELL( GND $  GND);

-- Node name is 'subout13' 
-- Equation name is 'subout13', location is LC018, type is output.
 subout13 = LCELL( GND $  GND);

-- Node name is 'subout20' 
-- Equation name is 'subout20', location is LC019, type is output.
 subout20 = LCELL( _EQ005 $  GND);
  _EQ005 = !incount0 &  incount1 &  incount2 &  incount3 & !incount4 & 
              _LC025 &  _X001
         #  incount0 & !incount2 &  incount3 & !incount4 &  _LC025 &  _X001
         #  incount0 & !incount3 & !incount4 &  _LC025 &  _X001
         # !incount0 & !incount3 &  incount4 &  _LC025 &  _X001;
  _X001  = EXP(!hour0 & !hour1 & !hour2 & !hour3 & !hour4);

-- Node name is 'subout21' 
-- Equation name is 'subout21', location is LC020, type is output.
 subout21 = LCELL( _EQ006 $  _EQ007);
  _EQ006 =  incount0 &  incount1 &  incount2 & !incount3 &  _LC025 &  _X001 & 
              _X003 &  _X004 &  _X005 &  _X006 &  _X007 &  _X008
         #  incount0 &  incount1 & !incount2 &  incount3 &  _LC025 &  _X001 & 
              _X003 &  _X004 &  _X005 &  _X006 &  _X007 &  _X008
         #  incount0 & !incount1 & !incount2 & !incount3 &  _LC025 &  _X001 & 
              _X003 &  _X004 &  _X005 &  _X006 &  _X007 &  _X008
         #  incount1 & !incount2 & !incount3 & !incount4 &  _LC025 &  _X001 & 
              _X003 &  _X004 &  _X005 &  _X006 &  _X007 &  _X008;
  _X001  = EXP(!hour0 & !hour1 & !hour2 & !hour3 & !hour4);
  _X003  = EXP(!incount1 &  incount2 &  incount3);
  _X004  = EXP(!incount1 &  incount4);
  _X005  = EXP(!incount0 & !incount1 &  incount3);
  _X006  = EXP(!incount0 & !incount1 &  incount2);
  _X007  = EXP( incount2 &  incount4);
  _X008  = EXP( incount3 &  incount4);
  _EQ007 =  _LC025 &  _X001 &  _X003 &  _X004 &  _X005 &  _X006 &  _X007 & 
              _X008;
  _X001  = EXP(!hour0 & !hour1 & !hour2 & !hour3 & !hour4);
  _X003  = EXP(!incount1 &  incount2 &  incount3);
  _X004  = EXP(!incount1 &  incount4);
  _X005  = EXP(!incount0 & !incount1 &  incount3);
  _X006  = EXP(!incount0 & !incount1 &  incount2);
  _X007  = EXP( incount2 &  incount4);
  _X008  = EXP( incount3 &  incount4);

-- Node name is 'subout22' 
-- Equation name is 'subout22', location is LC021, type is output.
 subout22 = LCELL( _EQ008 $  GND);
  _EQ008 = !incount0 & !incount1 & !incount2 &  incount3 & !incount4 & 
              _LC025 &  _X001
         #  incount0 &  incount2 & !incount3 & !incount4 &  _LC025 &  _X001
         # !incount1 & !incount2 & !incount3 &  incount4 &  _LC025 &  _X001
         #  incount1 &  incount2 & !incount4 &  _LC025 &  _X001;
  _X001  = EXP(!hour0 & !hour1 & !hour2 & !hour3 & !hour4);

-- Node name is 'subout23' 
-- Equation name is 'subout23', location is LC022, type is output.
 subout23 = LCELL( _EQ009 $  GND);
  _EQ009 =  incount0 & !incount1 &  incount2 &  incount3 & !incount4 & 
              _LC025 &  _X001
         #  incount0 &  incount1 & !incount2 & !incount3 & !incount4 & 
              _LC025 &  _X001
         # !incount0 & !incount1 &  incount2 & !incount3 & !incount4 & 
              _LC025 &  _X001;
  _X001  = EXP(!hour0 & !hour1 & !hour2 & !hour3 & !hour4);

-- Node name is 'subtringle' 
-- Equation name is 'subtringle', location is LC023, type is output.
 subtringle = LCELL( _EQ010 $  GND);
  _EQ010 = !hour0 & !hour1 & !hour2 & !hour3 & !hour4 &  _X008
         #  hour0 &  hour1 &  hour2 &  hour4 &  _X008
         #  incount0 &  incount1 & !incount2 & !incount3 &  incount4
         # !incount1 &  incount2 & !incount3 &  incount4
         #  hour3 &  hour4 &  _X008;
  _X008  = EXP( incount3 &  incount4);

-- Node name is ':66' from file "subroad.tdf" line 12, column 39
-- Equation name is '_LC025', type is buried 
_LC025   = LCELL( _EQ011 $  VCC);
  _EQ011 =  hour0 &  hour1 &  hour2 &  hour4
         #  hour3 &  hour4;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                     e:\traffic\subroad.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 11,711K