📄 subroad.rpt
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Project Information e:\traffic\subroad.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 03/30/2009 19:56:47
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
Untitled
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
subroad EPM7032LC44-6 10 12 0 13 8 40 %
User Pins: 10 12 0
Project Information e:\traffic\subroad.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Primitive 'subout13' is stuck at GND
Warning: Primitive 'subout12' is stuck at GND
Warning: Primitive 'subout11' is stuck at GND
Device-Specific Information: e:\traffic\subroad.rpt
subroad
***** Logic for device 'subroad' compiled without errors.
Device: EPM7032LC44-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
i i s s
n n u u
c c b b
o o h o o
u u o u u
n n u V G G G G G t t
t t r C N N N N N 1 1
3 4 0 C D D D D D 2 3
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
incount2 | 7 39 | subout20
incount1 | 8 38 | subout21
incount0 | 9 37 | subout22
GND | 10 36 | subout23
hour4 | 11 35 | VCC
hour3 | 12 EPM7032LC44-6 34 | subtringle
hour2 | 13 33 | subout11
hour1 | 14 32 | RESERVED
VCC | 15 31 | subout10
RESERVED | 16 30 | GND
RESERVED | 17 29 | subcol0
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
R R R R G V R R R s s
E E E E N C E E E u u
S S S S D C S S S b b
E E E E E E E c d
R R R R R R R o i
V V V V V V V l g
E E E E E E E 1 s
D D D D D D D e
l
e
c
t
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: e:\traffic\subroad.rpt
subroad
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 10/16( 62%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 13/16( 81%) 12/16( 75%) 12/16( 75%) 11/36( 30%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 22/32 ( 68%)
Total logic cells used: 13/32 ( 40%)
Total shareable expanders used: 8/32 ( 25%)
Total Turbo logic cells used: 13/32 ( 40%)
Total shareable expanders not available (n/a): 4/32 ( 12%)
Average fan-in: 7.84
Total fan-in: 102
Total input pins required: 10
Total output pins required: 12
Total bidirectional pins required: 0
Total logic cells required: 13
Total flipflops required: 0
Total product terms required: 52
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 8
Synthesized logic cells: 0/ 32 ( 0%)
Device-Specific Information: e:\traffic\subroad.rpt
subroad
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
4 (1) (A) INPUT 0 0 0 0 0 9 1 hour0
14 (10) (A) INPUT 0 0 0 0 0 9 1 hour1
13 (9) (A) INPUT 0 0 0 0 0 9 1 hour2
12 (8) (A) INPUT 0 0 0 0 0 9 1 hour3
11 (7) (A) INPUT 0 0 0 0 0 9 1 hour4
9 (6) (A) INPUT 0 0 0 0 0 8 0 incount0
8 (5) (A) INPUT 0 0 0 0 0 9 0 incount1
7 (4) (A) INPUT 0 0 0 0 0 9 0 incount2
6 (3) (A) INPUT 0 0 0 0 0 9 0 incount3
5 (2) (A) INPUT 0 0 0 0 0 9 0 incount4
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\traffic\subroad.rpt
subroad
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
29 27 B OUTPUT t 1 0 1 9 1 0 0 subcol0
27 29 B OUTPUT t 1 0 1 10 1 0 0 subcol1
28 28 B OUTPUT t 1 1 0 10 1 0 0 subdigselect
31 26 B OUTPUT t 1 0 0 10 1 0 0 subout10
33 24 B OUTPUT t 0 0 0 0 0 0 0 subout11
41 17 B OUTPUT t 0 0 0 0 0 0 0 subout12
40 18 B OUTPUT t 0 0 0 0 0 0 0 subout13
39 19 B OUTPUT t 1 1 0 10 1 0 0 subout20
38 20 B OUTPUT t 8 2 1 10 1 0 0 subout21
37 21 B OUTPUT t 1 1 0 10 1 0 0 subout22
36 22 B OUTPUT t 1 1 0 10 1 0 0 subout23
34 23 B OUTPUT t 2 1 1 10 0 0 0 subtringle
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\traffic\subroad.rpt
subroad
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(32) 25 B SOFT t 0 0 0 5 0 8 0 :66
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\traffic\subroad.rpt
subroad
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------- LC27 subcol0
| +----------------------- LC29 subcol1
| | +--------------------- LC28 subdigselect
| | | +------------------- LC26 subout10
| | | | +----------------- LC24 subout11
| | | | | +--------------- LC17 subout12
| | | | | | +------------- LC18 subout13
| | | | | | | +----------- LC19 subout20
| | | | | | | | +--------- LC20 subout21
| | | | | | | | | +------- LC21 subout22
| | | | | | | | | | +----- LC22 subout23
| | | | | | | | | | | +--- LC23 subtringle
| | | | | | | | | | | | +- LC25 :66
| | | | | | | | | | | | |
| | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC25 -> * * * * - - - * * * * - - | - * | <-- :66
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