select.rpt
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RPT
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Project Information e:\traffic\select.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 03/30/2009 19:14:23
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
Untitled
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
select EPM7064LC68-7 20 32 0 33 0 51 %
User Pins: 20 32 0
Device-Specific Information: e:\traffic\select.rpt
select
***** Logic for device 'select' compiled without errors.
Device: EPM7064LC68-7
Device Options:
Turbo Bit = ON
Security Bit = OFF
MultiVolt I/O = OFF
Device-Specific Information: e:\traffic\select.rpt
select
** ERROR SUMMARY **
Info: Chip 'select' in device 'EPM7064LC68-7' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
D D D D
A A A A
T T T T
V D D D A A A A
D D D D D C A A A D O O V O O
A A A A A C T T T A U U C U U
T T T G T T I A A A T G T T C T T
A A A N A A N 1 1 1 A N 0 0 I 1 1
5 4 3 D 1 8 T 5 6 0 9 D 4 5 O 3 1
-----------------------------------------------------_
/ 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 |
DATA6 | 10 60 | DATAOUT03
VCCIO | 11 59 | DATAOUT02
DATA7 | 12 58 | GND
DATA2 | 13 57 | DATAOUT12
maincol0 | 14 56 | DATAOUT06
maincol1 | 15 55 | DATAOUT15
GND | 16 54 | DATAOUT01
subcol0 | 17 53 | VCCIO
subcol1 | 18 EPM7064LC68-7 52 | DATAOUT14
DATAOUT116 | 19 51 | DATAOUT16
DATA11 | 20 50 | DATAOUT012
VCCIO | 21 49 | DATAOUT07
DATA12 | 22 48 | GND
DATAOUT015 | 23 47 | DATAOUT011
DATAOUT016 | 24 46 | DATAOUT111
DATA13 | 25 45 | DATAOUT112
GND | 26 44 | DATAOUT010
|_ 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 _|
------------------------------------------------------
D D D D V D D G V D D G D D D D V
A A A A C A A N C A A N A A A A C
T T T T C T T D C T T D T T T T C
A A A A I A A I A A A A A A I
1 O O O O O O N O O O O O O O
4 U U U U U T U U U U U U
T T T T T T T T T T T
0 1 1 1 0 1 1 1 1 0 0
1 1 1 1 1 8 7 9 1 8 9
3 3 4 5 4 0
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: e:\traffic\select.rpt
select
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 12/12(100%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 8/16( 50%) 12/12(100%) 8/16( 50%) 8/36( 22%)
C: LC33 - LC48 12/16( 75%) 12/12(100%) 12/16( 75%) 10/36( 27%)
D: LC49 - LC64 13/16( 81%) 12/12(100%) 12/16( 75%) 11/36( 30%)
Total dedicated input pins used: 4/4 (100%)
Total I/O pins used: 48/48 (100%)
Total logic cells used: 33/64 ( 51%)
Total shareable expanders used: 0/64 ( 0%)
Total Turbo logic cells used: 33/64 ( 51%)
Total shareable expanders not available (n/a): 32/64 ( 50%)
Average fan-in: 5.00
Total fan-in: 165
Total input pins required: 20
Total output pins required: 32
Total bidirectional pins required: 0
Total logic cells required: 33
Total flipflops required: 0
Total product terms required: 161
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 1/ 64 ( 1%)
Device-Specific Information: e:\traffic\select.rpt
select
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
5 (14) (A) INPUT 0 0 0 0 0 2 0 DATA1
13 (6) (A) INPUT 0 0 0 0 0 2 0 DATA2
7 (13) (A) INPUT 0 0 0 0 0 2 0 DATA3
8 (12) (A) INPUT 0 0 0 0 0 2 0 DATA4
9 (11) (A) INPUT 0 0 0 0 0 2 0 DATA5
10 (9) (A) INPUT 0 0 0 0 0 2 0 DATA6
12 (8) (A) INPUT 0 0 0 0 0 2 0 DATA7
4 (16) (A) INPUT 0 0 0 0 0 2 0 DATA8
67 - - INPUT 0 0 0 0 0 2 0 DATA9
68 - - INPUT 0 0 0 0 0 2 0 DATA10
20 (30) (B) INPUT 0 0 0 0 0 2 0 DATA11
22 (29) (B) INPUT 0 0 0 0 0 2 0 DATA12
25 (25) (B) INPUT 0 0 0 0 0 2 0 DATA13
27 (24) (B) INPUT 0 0 0 0 0 2 0 DATA14
2 - - INPUT 0 0 0 0 0 2 0 DATA15
1 - - INPUT 0 0 0 0 0 2 0 DATA16
14 (5) (A) INPUT 0 0 0 0 0 32 1 maincol0
15 (4) (A) INPUT 0 0 0 0 0 32 1 maincol1
17 (3) (A) INPUT 0 0 0 0 0 32 0 subcol0
18 (1) (A) INPUT 0 0 0 0 0 32 0 subcol1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\traffic\select.rpt
select
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
54 52 D OUTPUT t 1 0 1 5 0 0 0 DATAOUT01
59 57 D OUTPUT t 1 0 1 5 0 0 0 DATAOUT02
60 59 D OUTPUT t 1 0 1 5 0 0 0 DATAOUT03
65 64 D OUTPUT t 1 0 1 5 1 0 0 DATAOUT04
64 62 D OUTPUT t 1 0 1 5 1 0 0 DATAOUT05
56 54 D OUTPUT t 1 0 1 5 1 0 0 DATAOUT06
49 46 C OUTPUT t 1 0 1 5 0 0 0 DATAOUT07
41 38 C OUTPUT t 1 0 1 5 0 0 0 DATAOUT08
42 40 C OUTPUT t 1 0 1 5 0 0 0 DATAOUT09
44 41 C OUTPUT t 1 0 1 5 0 0 0 DATAOUT010
47 45 C OUTPUT t 1 0 1 5 0 0 0 DATAOUT011
61 60 D OUTPUT t 1 0 1 5 0 0 0 DATAOUT11
50 48 C OUTPUT t 1 0 1 5 0 0 0 DATAOUT012
57 56 D OUTPUT t 1 0 1 5 0 0 0 DATAOUT12
28 22 B OUTPUT t 1 0 1 5 0 0 0 DATAOUT013
62 61 D OUTPUT t 1 0 1 5 0 0 0 DATAOUT13
33 17 B OUTPUT t 1 0 1 5 0 0 0 DATAOUT014
52 51 D OUTPUT t 1 0 1 5 0 0 0 DATAOUT14
23 28 B OUTPUT t 1 0 1 5 0 0 0 DATAOUT015
55 53 D OUTPUT t 1 0 1 5 0 0 0 DATAOUT15
24 27 B OUTPUT t 1 0 1 5 0 0 0 DATAOUT016
51 49 D OUTPUT t 1 0 1 5 0 0 0 DATAOUT16
37 35 C OUTPUT t 1 0 1 5 0 0 0 DATAOUT17
36 33 C OUTPUT t 1 0 1 5 0 0 0 DATAOUT18
39 36 C OUTPUT t 1 0 1 5 0 0 0 DATAOUT19
40 37 C OUTPUT t 1 0 1 5 0 0 0 DATAOUT110
46 44 C OUTPUT t 1 0 1 5 0 0 0 DATAOUT111
45 43 C OUTPUT t 1 0 1 5 0 0 0 DATAOUT112
29 21 B OUTPUT t 1 0 1 5 0 0 0 DATAOUT113
30 20 B OUTPUT t 1 0 1 5 0 0 0 DATAOUT114
32 19 B OUTPUT t 1 0 1 5 0 0 0 DATAOUT115
19 32 B OUTPUT t 1 0 1 5 0 0 0 DATAOUT116
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\traffic\select.rpt
select
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 50 D SOFT s t 0 0 0 2 0 3 0 ~327~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\traffic\select.rpt
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