📄 cp15.lst
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107 {
108 unsigned int control;
109
110 control = _readControlRegister();
111
112 // Check if cache is disabled
113 if ((control & (1 << CP15_I_BIT)) == 0) {
114
115 control |= (1 << CP15_I_BIT);
116 _writeControlRegister(control);
117 TRACE_INFO("I cache enabled.\n\r");
118 }
119 #if !defined(OP_BOOTSTRAP_on)
120 else {
121
122 TRACE_INFO("I cache is already enabled.\n\r");
123 }
124 #endif
125 }
126
127 //------------------------------------------------------------------------------
128 /// Disable Instruction Cache
129 //------------------------------------------------------------------------------
130 void CP15_Disable_I_Cache(void)
131 {
132 unsigned int control;
133
134 control = _readControlRegister();
135
136 // Check if cache is enabled
137 if ((control & (1 << CP15_I_BIT)) != 0) {
138
139 control &= ~(1 << CP15_I_BIT);
140 _writeControlRegister(control);
141 TRACE_INFO("I cache disabled.\n\r");
142 }
143 else {
144
145 TRACE_INFO("I cache is already disabled.\n\r");
146 }
147 }
148
149 //------------------------------------------------------------------------------
150 /// Check MMU
151 /// \return 0 if MMU disable, 1 if MMU enable
152 //------------------------------------------------------------------------------
153 unsigned int CP15_Is_MMUEnabled(void)
154 {
155 unsigned int control;
156
157 control = _readControlRegister();
158 return ((control & (1 << CP15_M_BIT)) != 0);
159 }
160
161 //------------------------------------------------------------------------------
162 /// Enable MMU
163 //------------------------------------------------------------------------------
164 void CP15_EnableMMU(void)
165 {
166 unsigned int control;
167
168 control = _readControlRegister();
169
170 // Check if MMU is disabled
171 if ((control & (1 << CP15_M_BIT)) == 0) {
172
173 control |= (1 << CP15_M_BIT);
174 _writeControlRegister(control);
175 TRACE_INFO("MMU enabled.\n\r");
176 }
177 else {
178
179 TRACE_INFO("MMU is already enabled.\n\r");
180 }
181 }
182
183 //------------------------------------------------------------------------------
184 /// Disable MMU
185 //------------------------------------------------------------------------------
186 void CP15_DisableMMU(void)
187 {
188 unsigned int control;
189
190 control = _readControlRegister();
191
192 // Check if MMU is enabled
193 if ((control & (1 << CP15_M_BIT)) != 0) {
194
195 control &= ~(1 << CP15_M_BIT);
196 control &= ~(1 << CP15_C_BIT);
197 _writeControlRegister(control);
198 TRACE_INFO("MMU disabled.\n\r");
199 }
200 else {
201
202 TRACE_INFO("MMU is already disabled.\n\r");
203 }
204 }
205
206 //------------------------------------------------------------------------------
207 /// Check D_Cache
208 /// \return 0 if D_Cache disable, 1 if D_Cache enable (with MMU of course)
209 //------------------------------------------------------------------------------
210 unsigned int CP15_Is_DCacheEnabled(void)
211 {
212 unsigned int control;
213
214 control = _readControlRegister();
215 return ((control & ((1 << CP15_C_BIT)||(1 << CP15_M_BIT))) != 0);
216 }
217
218 //------------------------------------------------------------------------------
219 /// Enable Data Cache
220 //------------------------------------------------------------------------------
221 void CP15_Enable_D_Cache(void)
222 {
223 unsigned int control;
224
225 control = _readControlRegister();
226
227 if( !CP15_Is_MMUEnabled() ) {
228 TRACE_ERROR("Do nothing: MMU not enabled\n\r");
229 }
230 else {
231 // Check if cache is disabled
232 if ((control & (1 << CP15_C_BIT)) == 0) {
233
234 control |= (1 << CP15_C_BIT);
235 _writeControlRegister(control);
236 TRACE_INFO("D cache enabled.\n\r");
237 }
238 else {
239
240 TRACE_INFO("D cache is already enabled.\n\r");
241 }
242 }
243 }
244
245 //------------------------------------------------------------------------------
246 /// Disable Data Cache
247 //------------------------------------------------------------------------------
248 void CP15_Disable_D_Cache(void)
249 {
250 unsigned int control;
251
252 control = _readControlRegister();
253
254 // Check if cache is enabled
255 if ((control & (1 << CP15_C_BIT)) != 0) {
256
257 control &= ~(1 << CP15_C_BIT);
258 _writeControlRegister(control);
259 TRACE_INFO("D cache disabled.\n\r");
260 }
261 else {
262
263 TRACE_INFO("D cache is already disabled.\n\r");
264 }
265 }
266
267 #endif // CP15_PRESENT
268
0 bytes of memory
Errors: none
Warnings: none
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