📄 dsmlib.c
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{"bt/s", itBraDisp8 | itDelay, 0x8d00, 0xff00}, {"bf/s", itBraDisp8 | itDelay, 0x8f00, 0xff00},#if (CPU==SH7700 || CPU==SH7600) {"setrc", itOneReg, 0x8200, 0xff00}, {"ldrs", itGetDispPc, 0x8c00, 0xff00}, {"ldre", itGetDispPc, 0x8e00, 0xff00},#endif /* CPU==SH7700 || CPU==SH7600 */ {"mov.w", itGetRnAtDispPc, 0x9000, 0xf000}, {"bra", itBraDisp12 | itDelay, 0xa000, 0xf000}, {"bsr", itBraDisp12 | itDelay, 0xb000, 0xf000}, {"mov.b", itPutR0AtDispGbr, 0xc000, 0xff00}, {"mov.w", itPutR0AtDispGbr, 0xc100, 0xff00}, {"mov.l", itPutR0AtDispGbr, 0xc200, 0xff00}, {"trapa", itImm, 0xc300, 0xff00}, {"mov.b", itGetR0AtDispGbr, 0xc400, 0xff00}, {"mov.w", itGetR0AtDispGbr, 0xc500, 0xff00}, {"mov.l", itGetR0AtDispGbr, 0xc600, 0xff00}, {"mova", itMova, 0xc700, 0xff00}, {"tst", itImmToR0, 0xc800, 0xff00}, {"and", itImmToR0, 0xc900, 0xff00}, {"xor", itImmToR0, 0xca00, 0xff00}, {"or", itImmToR0, 0xcb00, 0xff00}, {"tst.b", itImmAtR0Gbr, 0xcc00, 0xff00}, {"and.b", itImmAtR0Gbr, 0xcd00, 0xff00}, {"xor.b", itImmAtR0Gbr, 0xce00, 0xff00}, {"or.b", itImmAtR0Gbr, 0xcf00, 0xff00}, {"mov.l", itGetRnAtDispPc, 0xd000, 0xf000}, {"mov", itImmToRn, 0xe000, 0xf000}, {"", 0, 0, 0} };#if (CPU==SH7750 || CPU==SH7700)LOCAL INST instFpp [] = { /* inst, instType, opcode, mask */ {"fabs", itOneFpReg, 0xf05d, 0xf0ff}, /* FABS FRn */ {"fadd", itTwoFpReg, 0xf000, 0xf00f}, /* FADD FRm,FRn */ {"fcmp/eq", itTwoFpReg, 0xf004, 0xf00f}, /* FCMP/EQ FRm,FRn */ {"fcmp/gt", itTwoFpReg, 0xf005, 0xf00f}, /* FCMP/GT FRm,FRn */ {"fdiv", itTwoFpReg, 0xf003, 0xf00f}, /* FDIV FRm,FRn */ {"fldi0", itOneFpReg, 0xf08d, 0xf0ff}, /* FLDI0 FRn */ {"fldi1", itOneFpReg, 0xf09d, 0xf0ff}, /* FLDI1 FRn */ {"flds", itFloadFpul, 0xf01d, 0xf0ff}, /* FLDS FRm,FPUL */ {"float", itFstoreFpul, 0xf02d, 0xf0ff}, /* FLOAT FPUL,FRn */ {"fmac", itThreeFpReg, 0xf00e, 0xf00f}, /* FMAC FR0,FRm,FRn */ {"fmov", itTwoFpReg, 0xf00c, 0xf00f}, /* FMOV FRm,FRn */ {"fmov.s", itGetFRnAtR0Rm, 0xf006, 0xf00f}, /* FMOV.S @(R0,Rm),FRn */ {"fmov.s", itPopFRn, 0xf009, 0xf00f}, /* FMOV.S @Rm+,FRn */ {"fmov.s", itGetFRnAtRm, 0xf008, 0xf00f}, /* FMOV.S @Rm,FRn */ {"fmov.s", itPutFRmAtR0Rn, 0xf007, 0xf00f}, /* FMOV.S FRm,@(R0,Rn) */ {"fmov.s", itPushFRm, 0xf00b, 0xf00f}, /* FMOV.S FRm,@-Rn */ {"fmov.s", itPutFRmAtRn, 0xf00a, 0xf00f}, /* FMOV.S FRm,@Rn */ {"fmul", itTwoFpReg, 0xf002, 0xf00f}, /* FMUL FRm,FRn */ {"fneg", itOneFpReg, 0xf04d, 0xf0ff}, /* FNEG FRn */ {"fsqrt", itOneFpReg, 0xf06d, 0xf0ff}, /* FSQRT FRn */ {"fsts", itFstoreFpul, 0xf00d, 0xf0ff}, /* FSTS FPUL,FRn */ {"fsub", itTwoFpReg, 0xf001, 0xf00f}, /* FSUB FRm,FRn */ {"ftrc", itFloadFpul, 0xf03d, 0xf0ff}, /* FTRC FRm,FPUL */ {"lds", itLoadFpscr, 0x406a, 0xf0ff}, /* LDS Rm,FPSCR */ {"lds", itLoadFpul, 0x405a, 0xf0ff}, /* LDS Rm,FPUL */ {"lds.l", itPopFpscr, 0x4066, 0xf0ff}, /* LDS.L @Rm+,FPSCR */ {"lds.l", itPopFpul, 0x4056, 0xf0ff}, /* LDS.L @Rm+,FPUL */ {"sts", itStoreFpscr, 0x006a, 0xf0ff}, /* STS FPSCR,Rn */ {"sts", itStoreFpul, 0x005a, 0xf0ff}, /* STS FPUL,Rn */ {"sts.l", itPushFpscr, 0x4062, 0xf0ff}, /* STS.L FPSCR,@-Rn */ {"sts.l", itPushFpul, 0x4052, 0xf0ff}, /* STS.L FPUL,@-Rn */#if (CPU==SH7750) /* SH7750 specific floating point and graphics support instructions */ {"fschg", itComplete, 0xf3fd, 0xffff}, /* FSCHG */ {"frchg", itComplete, 0xfbfd, 0xffff}, /* FRCHG */ {"ftrv", itFtrv, 0xf1fd, 0xf3ff}, /* FTRV XMTRX, FVn */ {"fipr", itFipr, 0xf0ed, 0xf0ff}, /* FIPR FVm, FVn */ {"fcnvsd", itConvToDp, 0xf0ad, 0xf1ff}, /* FCNVSD FPUL, DRn */ {"fcnvds", itConvToSp, 0xf0bd, 0xf1ff}, /* FCNVDS DRm, FPUL */#endif /* (CPU==SH7750) */ {"", 0, 0, 0} };#endif /* (CPU==SH7750 || CPU==SH7700) */#if (CPU==SH7700 || CPU==SH7600)/* * The list of SH DSP specific instructions. The first few are * 16 bit instructions (size is detected independently from this table), * all the rest are 32 bit. * All of these insns can be combined with parallel X & Y moves. * DSP instructions may have as many as 7 arguments encoded in * the lower three nibbles, and these are represented in the table by * the arglist. * The flags field handles "dct" and "dcf" prefixes and any infix * parallel mnemonics such as "pmuls", eg, "psub x, y, u pmuls e, f, g" */LOCAL SH_DSP_OPCODE_INFO instDsp[] = { /* inst, arglist, opcode, mask, flags*/ {"movs.l", {D_AS, D_DS}, 0xf402, 0xfc03, SH_MOVS}, {"movs.l", {D_DS, D_AS}, 0xf403, 0xfc03, SH_MOVS}, {"movs.w", {D_AS, D_DS}, 0xf400, 0xfc03, SH_MOVS}, {"movs.w", {D_DS, D_AS}, 0xf401, 0xfc03, SH_MOVS}, {"movx.w", {D_AX, D_DX}, 0xf000, 0xfc20, SH_MOVX}, {"movx.w", {D_DAX, D_AX}, 0xf020, 0xfc20, SH_MOVX}, {"movy.w", {D_AY, D_DY}, 0xf000, 0xfc10, SH_MOVY}, {"movy.w", {D_DAY, D_AY}, 0xf010, 0xfc10, SH_MOVY}, {"nopx", {0}, 0xf000, 0xfe5c, SH_MOVX}, {"nopy", {0}, 0xf000, 0xfda3, SH_MOVY}, {"pabs", {D_SX, D_DZ}, 0xf8008800, 0xfc00ff30}, {"pabs", {D_SY, D_DZ}, 0xf800a800, 0xfc00ffc0}, {"padd", {D_SX, D_SY, D_DU, D_SE, D_SF, D_DG}, 0xf8007000, 0xfc00f000, SH_PMULS}, {"padd", {D_SX, D_SY, D_DZ}, 0xf800b100, 0xfc00ff00}, {"padd", {D_SX, D_SY, D_DZ}, 0xf800b200, 0xfc00ff00, SH_DCT}, {"padd", {D_SX, D_SY, D_DZ}, 0xf800b300, 0xfc00ff00, SH_DCF}, {"paddc", {D_SX, D_SY, D_DZ}, 0xf800b000, 0xfc00ff00}, {"pand", {D_SX, D_SY, D_DZ}, 0xf8009500, 0xfc00ff00}, {"pand", {D_SX, D_SY, D_DZ}, 0xf8009600, 0xfc00ff00, SH_DCT}, {"pand", {D_SX, D_SY, D_DZ}, 0xf8009700, 0xfc00ff00, SH_DCF}, {"pclr", {D_DZ}, 0xf8008d00, 0xfc00fff0}, {"pclr", {D_DZ}, 0xf8008e00, 0xfc00fff0, SH_DCT}, {"pclr", {D_DZ}, 0xf8008f00, 0xfc00fff0, SH_DCF}, {"pcmp", {D_SX, D_SY}, 0xf8008400, 0xfc00ff0f}, {"pcopy", {D_SX, D_DZ}, 0xf800d900, 0xfc00ff30}, {"pcopy", {D_SY, D_DZ}, 0xf800f900, 0xfc00ffc0}, {"pcopy", {D_SX, D_DZ}, 0xf800da00, 0xfc00ff30, SH_DCT}, {"pcopy", {D_SY, D_DZ}, 0xf800fa00, 0xfc00ffc0, SH_DCT}, {"pcopy", {D_SX, D_DZ}, 0xf800db00, 0xfc00ff30, SH_DCF}, {"pcopy", {D_SY, D_DZ}, 0xf800fb00, 0xfc00ffc0, SH_DCF}, {"pdec", {D_SX, D_DZ}, 0xf8008900, 0xfc00ff30}, {"pdec", {D_SY, D_DZ}, 0xf800a900, 0xfc00ffc0}, {"pdec", {D_SX, D_DZ}, 0xf8008a00, 0xfc00ff30, SH_DCT}, {"pdec", {D_SY, D_DZ}, 0xf800aa00, 0xfc00ffc0, SH_DCT}, {"pdec", {D_SX, D_DZ}, 0xf8008b00, 0xfc00ff30, SH_DCF}, {"pdec", {D_SY, D_DZ}, 0xf800ab00, 0xfc00ffc0, SH_DCF}, {"pdmsb", {D_SX, D_DZ}, 0xf8009d00, 0xfc00ff30}, {"pdmsb", {D_SY, D_DZ}, 0xf800bd00, 0xfc00ffc0}, {"pdmsb", {D_SX, D_DZ}, 0xf8009e00, 0xfc00ff30, SH_DCT}, {"pdmsb", {D_SY, D_DZ}, 0xf800be00, 0xfc00ffc0, SH_DCT}, {"pdmsb", {D_SX, D_DZ}, 0xf8009f00, 0xfc00ff30, SH_DCF}, {"pdmsb", {D_SY, D_DZ}, 0xf800bf00, 0xfc00ffc0, SH_DCF}, {"pinc", {D_SX, D_DZ}, 0xf8009900, 0xfc00ff30}, {"pinc", {D_SY, D_DZ}, 0xf800b900, 0xfc00ffc0}, {"pinc", {D_SX, D_DZ}, 0xf8009a00, 0xfc00ff30, SH_DCT}, {"pinc", {D_SY, D_DZ}, 0xf800ba00, 0xfc00ffc0, SH_DCT}, {"pinc", {D_SX, D_DZ}, 0xf8009b00, 0xfc00ff30, SH_DCF}, {"pinc", {D_SY, D_DZ}, 0xf800bb00, 0xfc00ffc0, SH_DCF}, {"plds", {D_DZ, D_MACH}, 0xf800ed00, 0xfc00fff0}, {"plds", {D_DZ, D_MACL}, 0xf800fd00, 0xfc00fff0}, {"plds", {D_DZ, D_MACH}, 0xf800ee00, 0xfc00fff0, SH_DCT}, {"plds", {D_DZ, D_MACL}, 0xf800fe00, 0xfc00fff0, SH_DCT}, {"plds", {D_DZ, D_MACH}, 0xf800ef00, 0xfc00fff0, SH_DCF}, {"plds", {D_DZ, D_MACL}, 0xf800ff00, 0xfc00fff0, SH_DCF}, {"pmuls", {D_SE, D_SF, D_DG}, 0xf8004000, 0xfc00f0f3}, {"pneg", {D_SX, D_DZ}, 0xf800c900, 0xfc00ff30}, {"pneg", {D_SY, D_DZ}, 0xf800e900, 0xfc00ffc0}, {"pneg", {D_SX, D_DZ}, 0xf800ca00, 0xfc00ff30, SH_DCT}, {"pneg", {D_SY, D_DZ}, 0xf800ea00, 0xfc00ffc0, SH_DCT}, {"pneg", {D_SX, D_DZ}, 0xf800cb00, 0xfc00ff30, SH_DCF}, {"pneg", {D_SY, D_DZ}, 0xf800eb00, 0xfc00ffc0, SH_DCF}, {"por", {D_SX, D_SY, D_DZ}, 0xf800b500, 0xfc00ff00}, {"por", {D_SX, D_SY, D_DZ}, 0xf800b600, 0xfc00ff00, SH_DCT}, {"por", {D_SX, D_SY, D_DZ}, 0xf800b700, 0xfc00ff00, SH_DCF}, {"prnd", {D_SX, D_DZ}, 0xf8009800, 0xfc00ff30}, {"prnd", {D_SY, D_DZ}, 0xf800b800, 0xfc00ffc0}, {"psha", {D_SX, D_SY, D_DZ}, 0xf8009100, 0xfc00ff00}, {"psha", {D_SX, D_SY, D_DZ}, 0xf8009200, 0xfc00ff00, SH_DCT}, {"psha", {D_SX, D_SY, D_DZ}, 0xf8009300, 0xfc00ff00, SH_DCF}, {"psha", {D_IMM, D_DZ}, 0xf8001000, 0xfc00f800}, {"pshl", {D_SX, D_SY, D_DZ}, 0xf8008100, 0xfc00ff00}, {"pshl", {D_SX, D_SY, D_DZ}, 0xf8008200, 0xfc00ff00, SH_DCT}, {"pshl", {D_SX, D_SY, D_DZ}, 0xf8008300, 0xfc00ff00, SH_DCF}, {"pshl", {D_IMM, D_DZ}, 0xf8000000, 0xfc00f800}, {"psts", {D_MACH, D_DZ}, 0xf800cd00, 0xfc00fff0}, {"psts", {D_MACL, D_DZ}, 0xf800dd00, 0xfc00fff0}, {"psts", {D_MACH, D_DZ}, 0xf800ce00, 0xfc00fff0, SH_DCT}, {"psts", {D_MACL, D_DZ}, 0xf800de00, 0xfc00fff0, SH_DCT}, {"psts", {D_MACH, D_DZ}, 0xf800cf00, 0xfc00fff0, SH_DCF}, {"psts", {D_MACL, D_DZ}, 0xf800df00, 0xfc00fff0, SH_DCF}, {"psub", {D_SX, D_SY, D_DU, D_SE, D_SF, D_DG}, 0xf8006000, 0xfc00f000, SH_PMULS}, {"psub", {D_SX, D_SY, D_DZ}, 0xf800a100, 0xfc00ff00}, {"psub", {D_SX, D_SY, D_DZ}, 0xf800a200, 0xfc00ff00, SH_DCT}, {"psub", {D_SX, D_SY, D_DZ}, 0xf800a300, 0xfc00ff00, SH_DCF}, {"psubc", {D_SX, D_SY, D_DZ}, 0xf800a000, 0xfc00ff00}, {"pxor", {D_SX, D_SY, D_DZ}, 0xf800a500, 0xfc00ff00}, {"pxor", {D_SX, D_SY, D_DZ}, 0xf800a600, 0xfc00ff00, SH_DCT}, {"pxor", {D_SX, D_SY, D_DZ}, 0xf800a700, 0xfc00ff00, SH_DCF}, {0} };#endif /* CPU==SH7700 || CPU==SH7600 */ LOCAL BOOL delaySlot = FALSE; /* remember if next inst is in delayed slot */LOCAL int lastAddress = 0; /* remember the last address disassembled *//********************************************************************************* dsmFind - disassemble one instruction** This routine figures out which instruction is pointed to by binInst,* and returns a pointer to the INST which describes it.** RETURNS: pointer to instruction or NULL if unknown instruction.** INTERNAL* This routine, called by l(), disassembles the instruction that starts at the* address passed as an argument. It can be one machine-defined word for RISCs,* or the beginning of an array of words for CISCs. The return value is a pointer* to the instruction defined in the INST array. If no disassembly is possible,* the error number is set to S_dsmLib_UNKNOWN_INSTRUCTION and the return value* should be NULL. [Arch Port Kit]*/LOCAL INST *dsmFind ( USHORT binInst [] ) { FAST INST *iPtr; /* Find out which instruction it is */ for (iPtr = &inst [0]; iPtr->mask != 0; iPtr++) { if ((binInst [0] & iPtr->mask) == iPtr->op) return (iPtr); } /* If we're here, we couldn't find it */ errnoSet (S_dsmLib_UNKNOWN_INSTRUCTION); return (NULL); }/********************************************************************************* dsmPrint - print a disassembled instruction** This routine prints an instruction in disassembled form. It takes* as input a pointer to the instruction, a pointer to the INST* that describes it (as found by dsmFind()), and an address with which to* prepend the instruction.** INTERNAL* The actual printing of the instruction mnemonic and operands are done by this* function. The list of input arguments includes with the encoded instruction,* the return value of dsmFind(), the starting address of the instruction, the* number of instruction words, and pointer(s) to the function(s) that print* the parts of the instruction. [Arch Port Kit]** INTERNAL* The format of the disassembled output starts with the address and hexadecimal* representation of the instruction. The mnemonic and any instruction modifiers* typically follow, then the operands. The output should reflect the syntax of* the assembler input. Use spacing to align and enhance the readability of the* disassembly. [Arch Port Kit]*/LOCAL void dsmPrint ( USHORT binInst [], /* Pointer to instructin */ FAST INST *iPtr, /* Pointer to INST returned by dsmFind */ int address, /* Address with which to prepend instructin */ int nwords /* Instruction length, in words */ ) { FAST int ix; /* index into binInst */ FAST int wordsToPrint; /* # of 5-char areas to reserve for printing of hex version of instruction */ BOOL slotInst; /* TRUE if instruction is in delayed slot */ slotInst = (delaySlot == TRUE) && ((address - lastAddress) == 2); wordsToPrint = (((nwords - 1) / 2) + 1) * 2; /* Print the address and the instruction, in hex */ printf ("%06x ", address); for (ix = 0; ix < wordsToPrint; ++ix) /* print lines in multiples of 5 words */ { if ((ix > 0) && (ix % 3) == 0) /* print words on next line */ printf ("\n "); printf ((ix < nwords) ? "%04x " : " ", binInst [ix]); } if (slotInst) printf (" ("); else printf (" "); if (iPtr == NULL) { printf (".short 0x%04x", binInst[0]); delaySlot = FALSE; } else { char s[64 + MAX_SYS_SYM_LEN + 1]; /* Print the instruction mnemonic, the size code (.w, or whatever), and the arguments */ prtArgs (binInst, iPtr, address, s); printf ("%-10s %s", iPtr->name, s); if (iPtr->type & itDelay) delaySlot = TRUE; else delaySlot = FALSE; } if (slotInst) printf (")\n"); else printf ("\n"); lastAddress = address; }/********************************************************************************* prtArgs - format arguments** NOMANUAL*/LOCAL void prtArgs ( USHORT binInst [], /* Pointer to the binary instruction */ FAST INST *iPtr, /* Pointer to the INST describing binInst */ int address, /* Address at which the instruction resides */ char *s ) { UINT32 *dPtr; UINT32 addr; UINT16 disp; USHORT insn = binInst [0]; char ss[16]; switch (iPtr->type & itTypeMask) { case itComplete: s[0] = '\0';/* No arguments */ break; case itOneReg: sprintf (s, "r%u", (insn & 0x0f00) >> 8); break; case itStoreCsr: switch (iPtr->op) { case 0x0002: strcpy (ss, "sr"); break; case 0x0012: strcpy (ss, "gbr"); break; case 0x0022: strcpy (ss, "vbr"); break;#if (CPU==SH7750 || CPU==SH7700) case 0x0032: strcpy (ss, "ssr"); break; case 0x0042: strcpy (ss, "spc"); break; case 0x0082: strcpy (ss, "r0_bank"); break; case 0x0092: strcpy (ss, "r1_bank"); break; case 0x00a2: strcpy (ss, "r2_bank"); break; case 0x00b2: strcpy (ss, "r3_bank"); break; case 0x00c2: strcpy (ss, "r4_bank"); break; case 0x00d2: strcpy (ss, "r5_bank"); break; case 0x00e2: strcpy (ss, "r6_bank"); break; case 0x00f2: strcpy (ss, "r7_bank"); break;#endif /* CPU==SH7750 || CPU==SH7700 */ case 0x000a: strcpy (ss, "mach"); break; case 0x001a: strcpy (ss, "macl"); break; case 0x002a: strcpy (ss, "pr"); break;#if (CPU==SH7700 || CPU==SH7600) case 0x0052: strcpy (ss, "mod"); break; case 0x0062: strcpy (ss, "rs"); break; case 0x006a: strcpy (ss, "dsr"); break; case 0x0072: strcpy (ss, "re"); break; case 0x007a: strcpy (ss, "a0"); break; case 0x008a: strcpy (ss, "x0"); break;⌨️ 快捷键说明
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