dsmlib.c

vxworks5.5.1源代码。完整源代码

/* dsmLib.c - SH disassembler */

/* Copyright 1994-2001 Wind River Systems, Inc. */
#include "copyright_wrs.h"

/*
modification history
--------------------
02f,21feb02,h_k  fixed disassembler for "movx.w Da,@Ax*", "movy.w Da,@Ay*" and
                 "movy.w @Ay*,Dy" (SPR #73521).
02e,30oct01,jn   use symFindSymbol for symbol lookup (SPR #7453)
02d,29oct01,h_k  changed .word to .short for showing data length correctly in
                 Diab environment (SPR #69837).
02c,23nov00,hk   added ocbi, ocbp, ocbwb, and movca.l for SH7750.
02b,14nov00,zl   renamed some routines. Corrected dsmNBytes(), removed 
                 obsolete dsmCheck().
02a,24oct00,hk   added termination entry to instFpp[]. changed NULL to 0 for
		 non-pointer elements. added itComplete case to prtArgsFpp.
01z,17oct00,csi  Fixing the movs.l for disassembler
01y,13oct00,csi  Modification for DSP/FP disassemble
01x,15sep00,csi  Modification for DSP/FP disassemble
01w,26jun00,hk   changed to use disassembler in exception context.
		 fixed machine code for fschg/frchg.
01v,08jun99,zl   added SH4 (SH7750) graphics support instructions
01u,08mar99,hk   merged support for DSP & FPU.
01t,30oct98,kab  fix DSP psha insn.
01s,08aug98,kab  fix DSP movx insn.
01r,08jun98,knr  added support for SH7410.
01q,08may98,jmc  added support for SH-DSP and SH3-DSP.
01q,16jul98,st   added SH7750 support (only for SH7700 instructions).
01r,15jun98,hk   tweaked FPU instruction types.
01q,21nov97,st   added FPU instructions in inst table & prtArgs().
01p,07mar97,hk   changed PC/GBR relative offset display to hex. changed to use
                 lower-case letter. changed DC.W to .word. left shifted mnemonic
                 position. fixed PC relative operand display to 32bits.
01o,29jul96,hk   fixed 'mova' address display.
01n,21jun96,hk   added CPU==SH7700 control, fixed binary code typo in inst[]
		 and prtArgs(), changed itBraDispRn to itBraDispRm.
01m,20may96,ja   added new instructions in inst table & prtArgs().
01l,28jun95,hk   unified unknown operand printing to prtUnknownOperand().
01k,08mar95,hk   improved expression for a sign extended immediate value.
01j,30jan95,hk   changed itImmToRn display to hex style. copyright year 1995.
		 sign extend for "mov.w @(disp,pc),rn".
01i,13jan95,hk   fixed a word operand display bug in prtArgs().
01h,25dec94,hk   added dsmCheck() for dbgArchLib.
01g,25dec94,hk   added slot instruction indicator. improved address printing.
01f,08dec94,hk   modifying for better branch displacement display.
01e,06dec94,hk   modified itImmToRn case in prtArgs. #244 should be #-12.
01d,03dec94,hk   modified prtArgs() for itGetRnAtDispPc.
01c,01dec94,hk   added archPortKit docs. added dsmNbytes().
01b,26nov94,hk   fixed compilation error and warnings.
01a,25nov94,hk   written based on mc68k 03l.
*/

/*
This library contains everything necessary to print SH object code in
assembly language format.  The disassembly is done in Hitachi format.

The programming interface is via dsmInst(), which prints a single disassembled
instruction, and dsmNbytes(), which reports the size of an instruction.

To disassemble from the shell, use l(), which calls this
library to do the actual work.  See dbgLib() for details.

INCLUDE FILE: dsmLib.h

SEE ALSO: dbgLib

INTERNAL
The disassembler allows symbolic debugging at the assembly-language level on the
target. Header file definitions and structures supplemented with a few functions
are used to map hexadecimal values into user-readable mnemonics. The complexity
of the disassembler will vary with the size and bit field mapping of the inst-
ruction set. The few global routines are described below. Any other routines are
optional and may remain local. [Arch Port Kit]

INTERNAL
The _dbgArchInit routine (dbgArchLib) initializes a function pointer
_dbgDsmInstRtn (dbgLib) to point the dsmInst routine (dsmLib).

	l (addr, count)						--- dbgLib
	 \
	  dbgList (addr, count)					--- dbgLib
	   \
	    (*_dbgDsmInstRtn) (addr, (int)addr, dbgPrintAdrs)	--- dbgLib
	     \
	      dsmInst (binInst, address, prtAddress)		--- dsmLib

Namely, dsmInst() is the entry point of this library.  Also, a pointer to
dbgPrintAdrs (dbgLib) is passed to dsmInst(), as the default address printing
routine.
*/

#include "vxWorks.h"
#include "dsmLib.h"
#include "symLib.h"
#include "sysSymTbl.h"
#include "string.h"
#include "stdio.h"
#include "errnoLib.h"
#include "cplusLib.h"

/* forward LOCAL functions */

LOCAL INST *dsmFind (USHORT binInst []);
LOCAL void prtArgs (USHORT binInst [], INST *iPtr, int address, char *s);
LOCAL void dsmFormatAdrs (int address, char *s);
LOCAL void nPrtAddress (int address);

#if (CPU==SH7700 || CPU==SH7750)
/* Added for DSP/FP disassembler */
LOCAL INST *dsmFindFpp (USHORT fppInst []);
LOCAL void dsmPrintFpp (USHORT fppInst [], INST *fppPtr, int address,
			int nwords); 
LOCAL void prtArgsFpp (USHORT fppInst [], INST *fppPtr, int address,
		       char *s); 
#endif /* (CPU==SH7700 || CPU==SH7750) */

extern STATUS dspProbe (void);
extern STATUS fppProbe (void);

/*
This table is ordered by the number of bits in an instruction's
one word mask, beginning with the greatest number of bits in mask.
This scheme is used for avoiding conflicts between instructions
when matching bit patterns.  The instruction ops are arranged
sequentially within each group of instructions for a particular
mask so that uniqueness can be easily spotted.

INTERNAL
The primary structure of the disassembler is this array of instruction
mnemonics, instruction types, opcodes, and opcode masks. The type definition
of the INST structure may vary with each architecture, but should be similar
to the example shown in h/arch/<arch>/dsm<Arch>Lib.h. Additional opcodes and
masks are often useful in the disassembly process. This array of structures
is usually quite big, especially for CISC processors. [Arch Port Kit]

INTERNAL
Use additional structures for the register names and encoding, sub-opcode
tables, and other bit-field encoding that are useful in disassembly. The
content and number of structures should be derived naturally from the
instruction encoding tables. The software design should mimic the hardware
that decodes instructions. [Arch Port Kit]
*/

LOCAL INST inst [] =
    {
    /* inst,	instType,		opcode,	mask	*/
    {"clrt",	itComplete,		0x0008,	0xffff},
    {"nop",	itComplete,		0x0009,	0xffff},
    {"rts",	itComplete | itDelay,	0x000b,	0xffff},
    {"sett",	itComplete,		0x0018,	0xffff},
    {"div0u",	itComplete,		0x0019,	0xffff},
    {"sleep",	itComplete,		0x001b,	0xffff},
    {"clrmac",	itComplete,		0x0028,	0xffff},
    {"rte",	itComplete | itDelay,	0x002b,	0xffff},
#if (CPU==SH7750 || CPU==SH7700)
    {"ldtlb",	itComplete,		0x0038,	0xffff},
    {"clrs",	itComplete,		0x0048,	0xffff},
    {"sets",	itComplete,		0x0058,	0xffff},
#endif /* CPU==SH7750 || CPU==SH7700 */
    {"stc",	itStoreCsr,		0x0002,	0xf0ff}, /* STC   SR,  Rn */
    {"bsrf",	itBraDispRm | itDelay,	0x0003,	0xf0ff},
    {"sts",	itStoreCsr,		0x000a,	0xf0ff}, /* STS   MACH,Rn */
    {"stc",	itStoreCsr,		0x0012,	0xf0ff}, /* STC   GBR, Rn */
    {"sts",	itStoreCsr,		0x001a,	0xf0ff}, /* STS   MACL,Rn */
    {"stc",	itStoreCsr,		0x0022,	0xf0ff}, /* STC   VBR, Rn */
    {"braf",	itBraDispRm | itDelay,	0x0023,	0xf0ff},
    {"movt",	itOneReg,		0x0029,	0xf0ff},
    {"sts",	itStoreCsr,		0x002a,	0xf0ff}, /* STS   PR,  Rn */
#if (CPU==SH7700 || CPU==SH7600)
    {"stc",	itStoreCsr,	       	0x0052, 0xf0ff},
    {"stc",	itStoreCsr,	       	0x0062, 0xf0ff},
    {"stc",	itStoreCsr,	       	0x0072, 0xf0ff},
    {"sts",	itStoreCsr,	       	0x006a, 0xf0ff},    
    {"sts",	itStoreCsr,	       	0x007a, 0xf0ff},
    {"sts",	itStoreCsr,	       	0x008a, 0xf0ff},
    {"sts",	itStoreCsr,	       	0x009a, 0xf0ff},
    {"sts",	itStoreCsr,	       	0x00aa, 0xf0ff},
    {"sts",	itStoreCsr,	       	0x00ba, 0xf0ff},
#endif /* CPU==SH7700 || CPU==SH7600 */
#if (CPU==SH7750 || CPU==SH7700)
    {"stc",	itStoreCsr,		0x0032,	0xf0ff}, /* STC   SSR, Rn    */
    {"stc",	itStoreCsr,		0x0042,	0xf0ff}, /* STC   SPC, Rn    */
    {"stc",	itStoreCsr,		0x0082,	0xf0ff}, /* STC   R0_BANK,Rn */
    {"pref",	itAtOneReg,		0x0083,	0xf0ff}, /* PREF  @Rm        */
    {"stc",	itStoreCsr,		0x0092,	0xf0ff}, /* STC   R1_BANK,Rn */
    {"stc",	itStoreCsr,		0x00a2,	0xf0ff}, /* STC   R2_BANK,Rn */
    {"stc",	itStoreCsr,		0x00b2,	0xf0ff}, /* STC   R3_BANK,Rn */
    {"stc",	itStoreCsr,		0x00c2,	0xf0ff}, /* STC   R4_BANK,Rn */
    {"stc",	itStoreCsr,		0x00d2,	0xf0ff}, /* STC   R5_BANK,Rn */
    {"stc",	itStoreCsr,		0x00e2,	0xf0ff}, /* STC   R6_BANK,Rn */
    {"stc",	itStoreCsr,		0x00f2,	0xf0ff}, /* STC   R7_BANK,Rn */
#endif /* CPU==SH7750 || CPU==SH7700 */
#if (CPU==SH7750)
    {"ocbi",	itAtOneReg,		0x0093,	0xf0ff}, /* OCBI    @Rn */
    {"ocbp",	itAtOneReg,		0x00a3,	0xf0ff}, /* OCBP    @Rn */
    {"ocbwb",	itAtOneReg,		0x00b3,	0xf0ff}, /* OCBWB   @Rn */
    {"movca.l",	itAtOneReg,		0x00c3,	0xf0ff}, /* MOVCA.L R0,@Rn */
#endif /* CPU==SH7750 */
    {"mov.b",	itPutRmAtR0Rn,		0x0004,	0xf00f},
    {"mov.w",	itPutRmAtR0Rn,		0x0005,	0xf00f},
    {"mov.l",	itPutRmAtR0Rn,		0x0006,	0xf00f},
    {"mul.l",	itTwoReg,		0x0007,	0xf00f},
    {"mov.b",	itGetRnAtR0Rm,		0x000c,	0xf00f},
    {"mov.w",	itGetRnAtR0Rm,		0x000d,	0xf00f},
    {"mov.l",	itGetRnAtR0Rm,		0x000e,	0xf00f},
    {"mac.l",	itMac,			0x000f,	0xf00f},
    {"mov.l",	itPutRmAtDispRn,	0x1000,	0xf000},
    {"mov.b",	itPutRmAtRn,		0x2000,	0xf00f},
    {"mov.w",	itPutRmAtRn,		0x2001,	0xf00f},
    {"mov.l",	itPutRmAtRn,		0x2002,	0xf00f},
    {"mov.b",	itPushReg,		0x2004,	0xf00f},
    {"mov.w",	itPushReg,		0x2005,	0xf00f},
    {"mov.l",	itPushReg,		0x2006,	0xf00f},
    {"div0s",	itTwoReg,		0x2007,	0xf00f},
    {"tst",	itTwoReg,		0x2008,	0xf00f},
    {"and",	itTwoReg,		0x2009,	0xf00f},
    {"xor",	itTwoReg,		0x200a,	0xf00f},
    {"or",	itTwoReg,		0x200b,	0xf00f},
    {"cmp/str",	itTwoReg,		0x200c,	0xf00f},
    {"xtrct",	itTwoReg,		0x200d,	0xf00f},
    {"mulu.w",	itTwoReg,		0x200e,	0xf00f},
    {"muls.w",	itTwoReg,		0x200f,	0xf00f},
    {"cmp/eq",	itTwoReg,		0x3000,	0xf00f},
    {"cmp/hs",	itTwoReg,		0x3002,	0xf00f},
    {"cmp/ge",	itTwoReg,		0x3003,	0xf00f},
    {"div1",	itTwoReg,		0x3004,	0xf00f},
    {"dmulu.l",	itTwoReg,		0x3005,	0xf00f},
    {"cmp/hi",	itTwoReg,		0x3006,	0xf00f},
    {"cmp/gt",	itTwoReg,		0x3007,	0xf00f},
    {"sub",	itTwoReg,		0x3008,	0xf00f},
    {"subc",	itTwoReg,		0x300a,	0xf00f},
    {"subv",	itTwoReg,		0x300b,	0xf00f},
    {"add",	itTwoReg,		0x300c,	0xf00f},
    {"dmuls.l",	itTwoReg,		0x300d,	0xf00f},
    {"addc",	itTwoReg,		0x300e,	0xf00f},
    {"addv",	itTwoReg,		0x300f,	0xf00f},
    {"shll",	itOneReg,		0x4000,	0xf0ff},
    {"shlr",	itOneReg,		0x4001,	0xf0ff},
    {"sts.l",	itPushCsr,		0x4002,	0xf0ff},
    {"stc.l",	itPushCsr,		0x4003,	0xf0ff},
    {"rotl",	itOneReg,		0x4004,	0xf0ff},
    {"rotr",	itOneReg,		0x4005,	0xf0ff},
    {"lds.l",	itPopCsr,		0x4006,	0xf0ff},
    {"ldc.l",	itPopCsr,		0x4007,	0xf0ff},
    {"shll2",	itOneReg,		0x4008,	0xf0ff},
    {"shlr2",	itOneReg,		0x4009,	0xf0ff},
    {"lds",	itLoadCsr,		0x400a,	0xf0ff},
    {"jsr",	itAtOneReg | itDelay,	0x400b,	0xf0ff},
    {"ldc",	itLoadCsr,		0x400e,	0xf0ff},
    {"dt",	itOneReg,		0x4010,	0xf0ff},
    {"cmp/pz",	itOneReg,		0x4011,	0xf0ff},
    {"sts.l",	itPushCsr,		0x4012,	0xf0ff},
    {"stc.l",	itPushCsr,		0x4013,	0xf0ff},
#if (CPU==SH7700 || CPU==SH7600)
    {"setrc",	itOneReg,		0x4014,	0xf0ff},
#endif /* CPU==SH7700 || CPU==SH7600 */
    {"cmp/pl",	itOneReg,		0x4015,	0xf0ff},
    {"lds.l",	itPopCsr,		0x4016,	0xf0ff},
    {"ldc.l",	itPopCsr,		0x4017,	0xf0ff},
    {"shll8",	itOneReg,		0x4018,	0xf0ff},
    {"shlr8",	itOneReg,		0x4019,	0xf0ff},
    {"lds",	itLoadCsr,		0x401a,	0xf0ff},
    {"tas.b",	itAtOneReg,		0x401b,	0xf0ff},
    {"ldc",	itLoadCsr,		0x401e,	0xf0ff},
    {"shal",	itOneReg,		0x4020,	0xf0ff},
    {"shar",	itOneReg,		0x4021,	0xf0ff},
    {"sts.l",	itPushCsr,		0x4022,	0xf0ff},
    {"stc.l",	itPushCsr,		0x4023,	0xf0ff},
    {"rotcl",	itOneReg,		0x4024,	0xf0ff},
    {"rotcr",	itOneReg,		0x4025,	0xf0ff},
    {"lds.l",	itPopCsr,		0x4026,	0xf0ff},
    {"ldc.l",	itPopCsr,		0x4027,	0xf0ff},
    {"shll16",	itOneReg,		0x4028,	0xf0ff},
    {"shlr16",	itOneReg,		0x4029,	0xf0ff},
    {"lds",	itLoadCsr,		0x402a,	0xf0ff},
    {"jmp",	itAtOneReg | itDelay,	0x402b,	0xf0ff},
    {"ldc",	itLoadCsr,		0x402e,	0xf0ff},
#if (CPU==SH7700 || CPU==SH7600)
    {"stc.l",	itPushCsr,	       	0x4053, 0xf0ff},
    {"ldc.l",	itPopCsr,	       	0x4057, 0xf0ff},
    {"sts.l",	itPushCsr,	       	0x4062, 0xf0ff},
    {"stc.l",	itPushCsr,	       	0x4063, 0xf0ff},
    {"lds.l",	itPopCsr,	       	0x4066, 0xf0ff},
    {"ldc.l",	itPopCsr,	       	0x4067, 0xf0ff},
    {"stc.l",	itPushCsr,	       	0x4073, 0xf0ff},
    {"sts.l",	itPushCsr,	       	0x4072, 0xf0ff},
    {"lds.l",	itPopCsr,	       	0x4076, 0xf0ff},
    {"ldc.l",	itPopCsr,	       	0x4077, 0xf0ff},
    {"sts.l",	itPushCsr,	       	0x4082, 0xf0ff}, 
    {"lds.l",	itPopCsr,	       	0x4086, 0xf0ff},
    {"sts.l",	itPushCsr,	       	0x4092, 0xf0ff},
    {"lds.l",	itPopCsr,	       	0x4096, 0xf0ff},
    {"lds",	itLoadCsr,	       	0x406a, 0xf0ff},
    {"lds",	itLoadCsr,	       	0x407a, 0xf0ff},
    {"lds",	itLoadCsr,	       	0x408a, 0xf0ff},
    {"lds",	itLoadCsr,	       	0x409a, 0xf0ff},
    {"ldc",	itLoadCsr,	       	0x405e, 0xf0ff},
    {"ldc",	itLoadCsr,	       	0x407e, 0xf0ff},
    {"ldc",	itLoadCsr,	       	0x406e, 0xf0ff},
    {"sts.l",	itPushCsr,	       	0x40a2, 0xf0ff},
    {"lds.l",	itPopCsr,	       	0x40a6, 0xf0ff},
    {"lds",	itLoadCsr,	       	0x40aa, 0xf0ff},
    {"sts.l",	itPushCsr,	       	0x40b2, 0xf0ff},
    {"lds.l",	itPopCsr,	       	0x40b6, 0xf0ff}, 
    {"lds",	itLoadCsr,	       	0x40ba, 0xf0ff},  
#endif /* CPU==SH7700 || CPU==SH7600 */
#if (CPU==SH7750 || CPU==SH7700)
    {"stc.l",	itPushCsr,	0x4033,	0xf0ff}, /* STC.L  SSR,@-Rn */
    {"ldc.l",	itPopCsr,	0x4037,	0xf0ff}, /* LDC.L  @Rm+,SSR */
    {"ldc",	itLoadCsr,	0x403e,	0xf0ff}, /* LDC    Rm,SSR */
    {"stc.l",	itPushCsr,	0x4043,	0xf0ff}, /* STC.L  SPC,@-Rn */
    {"ldc.l",	itPopCsr,	0x4047,	0xf0ff}, /* LDC.L  @Rm+,SPC */
    {"ldc",	itLoadCsr,	0x404e,	0xf0ff}, /* LDC    Rm,SPC */
    {"stc.l",	itPushCsr,	0x4083,	0xf0ff}, /* STC.L  R0_BANK,@-Rn */
    {"ldc.l",	itPopCsr,	0x4087,	0xf0ff}, /* LDC.L  @Rm+,R0_BANK */
    {"ldc",	itLoadCsr,	0x408e,	0xf0ff}, /* LDC    Rm,R0_BANK */
    {"stc.l",	itPushCsr,	0x4093,	0xf0ff}, /* STC.L  R1_BANK,@-Rn */
    {"ldc.l",	itPopCsr,	0x4097,	0xf0ff}, /* LDC.L  @Rm+,R1_BANK */
    {"ldc",	itLoadCsr,	0x409e,	0xf0ff}, /* LDC    Rm,R1_BANK */
    {"stc.l",	itPushCsr,	0x40a3,	0xf0ff}, /* STC.L  R2_BANK,@-Rn */
    {"ldc.l",	itPopCsr,	0x40a7,	0xf0ff}, /* LDC.L  @Rm+,R2_BANK */
    {"ldc",	itLoadCsr,	0x40ae,	0xf0ff}, /* LDC    Rm,R2_BANK */
    {"stc.l",	itPushCsr,	0x40b3,	0xf0ff}, /* STC.L  R3_BANK,@-Rn */
    {"ldc.l",	itPopCsr,	0x40b7,	0xf0ff}, /* LDC.L  @Rm+,R3_BANK */
    {"ldc",	itLoadCsr,	0x40be,	0xf0ff}, /* LDC    Rm,R3_BANK */
    {"stc.l",	itPushCsr,	0x40c3,	0xf0ff}, /* STC.L  R4_BANK,@-Rn */
    {"ldc.l",	itPopCsr,	0x40c7,	0xf0ff}, /* LDC.L  @Rm+,R4_BANK */
    {"ldc",	itLoadCsr,	0x40ce,	0xf0ff}, /* LDC    Rm,R4_BANK */
    {"stc.l",	itPushCsr,	0x40d3,	0xf0ff}, /* STC.L  R5_BANK,@-Rn */
    {"ldc.l",	itPopCsr,	0x40d7,	0xf0ff}, /* LDC.L  @Rm+,R5_BANK */
    {"ldc",	itLoadCsr,	0x40de,	0xf0ff}, /* LDC    Rm,R5_BANK */
    {"stc.l",	itPushCsr,	0x40e3,	0xf0ff}, /* STC.L  R6_BANK,@-Rn */
    {"ldc.l",	itPopCsr,	0x40e7,	0xf0ff}, /* LDC.L  @Rm+,R6_BANK */
    {"ldc",	itLoadCsr,	0x40ee,	0xf0ff}, /* LDC    Rm,R6_BANK */
    {"stc.l",	itPushCsr,	0x40f3,	0xf0ff}, /* STC.L  R7_BANK,@-Rn */
    {"ldc.l",	itPopCsr,	0x40f7,	0xf0ff}, /* LDC.L  @Rm+,R7_BANK */
    {"ldc",	itLoadCsr,	0x40fe,	0xf0ff}, /* LDC    Rm,R7_BANK */
    {"shad",	itTwoReg,	0x400c,	0xf00f}, /* SHAD   Rm,Rn */
    {"shld",	itTwoReg,	0x400d,	0xf00f}, /* SHLD   Rm,Rn */
#endif /* CPU==SH7750 || CPU==SH7700 */
    {"mac.w",	itMac,			0x400f,	0xf00f},
    {"mov.l",	itGetRnAtDispRm,	0x5000,	0xf000},
    {"mov.b",	itGetRnAtRm,		0x6000,	0xf00f},
    {"mov.w",	itGetRnAtRm,		0x6001,	0xf00f},
    {"mov.l",	itGetRnAtRm,		0x6002,	0xf00f},
    {"mov",	itTwoReg,		0x6003,	0xf00f},
    {"mov.b",	itPopReg,		0x6004,	0xf00f},
    {"mov.w",	itPopReg,		0x6005,	0xf00f},
    {"mov.l",	itPopReg,		0x6006,	0xf00f},
    {"not",	itTwoReg,		0x6007,	0xf00f},
    {"swap.b",	itTwoReg,		0x6008,	0xf00f},
    {"swap.w",	itTwoReg,		0x6009,	0xf00f},
    {"negc",	itTwoReg,		0x600a,	0xf00f},
    {"neg",	itTwoReg,		0x600b,	0xf00f},
    {"extu.b",	itTwoReg,		0x600c,	0xf00f},
    {"extu.w",	itTwoReg,		0x600d,	0xf00f},
    {"exts.b",	itTwoReg,		0x600e,	0xf00f},
    {"exts.w",	itTwoReg,		0x600f,	0xf00f},
    {"add",	itImmToRn,		0x7000,	0xf000},
    {"mov.b",	itPutR0AtDispRn,	0x8000,	0xff00},
    {"mov.w",	itPutR0AtDispRn,	0x8100,	0xff00},
    {"mov.b",	itGetR0AtDispRm,	0x8400,	0xff00},
    {"mov.w",	itGetR0AtDispRm,	0x8500,	0xff00},
    {"cmp/eq",	itImmToR0,		0x8800,	0xff00},
    {"bt",	itBraDisp8,		0x8900,	0xff00},
    {"bf",	itBraDisp8,		0x8b00,	0xff00},