xlli_plato_defs.inc

Windows CE 6.0 BSP for VOIP sample phone. Intel PXA270 platform.

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; Copyright (c) Microsoft Corporation.  All rights reserved.
;
;
; Use of this sample source code is subject to the terms of the Microsoft
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; you did not accept the terms of the license agreement, you are not
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; THE SAMPLE SOURCE CODE IS PROVIDED "AS IS", WITH NO WARRANTIES OR INDEMNITIES.
;
;*********************************************************************************
;
;        COPYRIGHT (c) 2002 - 2004 Intel Corporation
;
;   The information in this file is furnished for informational use only,
;   is subject to change without notice, and should not be construed as
;   a commitment by Intel Corporation. Intel Corporation assumes no
;   responsibility or liability for any errors or inaccuracies that may appear
;   in this document or any software that may be provided in association with
;   this document.
;
;*********************************************************************************
;
;  FILENAME:       xlli_plato_defs.inc (Platform specific addresses and
;                  defalut values for Plato platform bring up)
;
; LAST MODIFIED:   13-Feb-2004
;
;******************************************************************************
;
;
; Include file for Plato specific Cross Platform Low Level Initialization (XLLI)
;


;
; Platform specific bits
;
xlli_SYS_RESET                       EQU    (0x01)   ; System reset bit

;
; platform GPIO pin settings (Bulverde/Plato)
;
xlli_GPSR0_value          EQU   (0x00100000)   ; Set GPIO Pin Output Set register
xlli_GPSR1_value          EQU   (0x00000000)   
xlli_GPSR2_value          EQU   (0x04010000)  
xlli_GPSR3_value          EQU   (0x00020000)

xlli_GPCR0_value          EQU   (0xC0A8A800)   ; Clear registers
xlli_GPCR1_value          EQU   (0xFC008EF8)   ; FFUART related
xlli_GPCR2_value          EQU   (0x1BEAFFFF)
xlli_GPCR3_value          EQU   (0x0065FF01)

xlli_GRER0_value          EQU   (0x00000000)   ; Rising Edge Detect
xlli_GRER1_value          EQU   (0x00000000)
xlli_GRER2_value          EQU   (0x00000000)
xlli_GRER3_value          EQU   (0x00000000)

xlli_GFER0_value          EQU   (0x00000000)   ; Falling Edge Detect
xlli_GFER1_value          EQU   (0x00000000)
xlli_GFER2_value          EQU   (0x00000000)
xlli_GFER3_value          EQU   (0x00000000)

xlli_GPLR0_value          EQU   (0x00000000)   ; Pin Level Registers
xlli_GPLR1_value          EQU   (0x00000000)
xlli_GPLR2_value          EQU   (0x00000000)
xlli_GPLR3_value          EQU   (0x00000000)

xlli_GEDR0_value          EQU   (0x00000000)   ; Edge Detect Status
xlli_GEDR1_value          EQU   (0x00000000)
xlli_GEDR2_value          EQU   (0x00000000)
xlli_GEDR3_value          EQU   (0x00000000)

xlli_GPDR0_value          EQU   (0xC0B9A800)   ; Direction Registers
xlli_GPDR1_value          EQU   (0xFCEF8EFB)
xlli_GPDR2_value          EQU   (0x0FFB7FFF)  ; potential hang. old value = (0x0FFB7FFF)new value = (0x0FFBFFFF)
xlli_GPDR3_value          EQU   (0x006DFF01)

xlli_GAFR0_L_value        EQU  (0x02000000)   ; Alternate function registers
xlli_GAFR0_U_value        EQU  (0xA5E54198)
xlli_GAFR1_L_value        EQU  (0x6001AA12)
xlli_GAFR1_U_value        EQU  (0xAAA5A1AA)
xlli_GAFR2_L_value        EQU  (0x0AAAAAAA)  ;potential hang. old value = (0x0AAAAAAA) new value = (0x4AAAAAAA)
xlli_GAFR2_U_value        EQU  (0x21A00556) 
xlli_GAFR3_L_value        EQU  (0x56AA557F)
xlli_GAFR3_U_value        EQU  (0x00001559)


;
; Core Frequency settings for Plato
;

; ----------------------------------------------------------------------------
; SAMPLE SETTINGS
; ----------------------------------------------------------------------------
; Core freq = 104MHz, Run Mode = 104MHz, System Bus = 104MHz, MEM_CLK = 104MHz
;xlli_PLATO_CLK_DATA EQU  (0x02000308); A=1, 2N=6, L=8
;xlli_PLATO_CLKCFG_DATA EQU  (0x8); B=1


; Core freq = 312Hz (Half-Turbo), Run Mode = 208MHz, System Bus = 104MHz, MEM_CLK = 104MHz
;xlli_PLATO_CLK_DATA EQU  (0x00000310); A=0, 2N=6, L=16
;xlli_PLATO_CLKCFG_DATA EQU  (0x4); B=0, HT=1

; Core freq = 312Hz (Half-Turbo), Run Mode = 208MHz, System Bus = 208MHz, MEM_CLK = 104MHz
;xlli_PLATO_CLK_DATA EQU  (0x00000310); A=0, 2N=6, L=16
;xlli_PLATO_CLKCFG_DATA EQU  (0xC); B=1, HT=1

; ----------------------------------------------------------------------------
; CURRENT SETTINGS
; ----------------------------------------------------------------------------
; Core freq = 208Hz , Run Mode = 208MHz, System Bus = 208MHz, MEM_CLK = 104MHz
xlli_PLATO_CLK_DATA EQU  (0x00000310); A=0, 2N=6, L=16
xlli_PLATO_CLKCFG_DATA EQU  (0x8); B=1


;
; MEMORY CONTROLLER SETTINGS FOR Plato
;

xlli_MDREFR_value  EQU   (0x0000001E); old value - 0x0000001E
xlli_MSC0_value    EQU   (0x7FF07FF0)     ; Bulverde on chip Flash value
xlli_MSC1_value    EQU   (0x0000CCD1)
xlli_MSC2_value    EQU   (0x00007FF8)
xlli_MECR_value    EQU   (0x00000000)
xlli_MCMEM0_value  EQU   (0x00014307)
xlli_MCMEM1_value  EQU   (0x00014307)
xlli_MCATT0_value  EQU   (0x0001C787)
xlli_MCATT1_value  EQU   (0x0001C787)
xlli_MCIO0_value   EQU   (0x0001430F)
xlli_MCIO1_value   EQU   (0x0001430F)
xlli_FLYCNFG_value EQU   (0x00010001)
xlli_MDMRSLP_value EQU   (0x0000C000)
xlli_SXCNFG_value  EQU   (0x40044004)   ; Default value at boot up
xlli_MSC1_update   EQU   (0x0000CCD1)   ; Run value


; SDRAM Settings

xlli_MDCNFG_value  EQU   (0x0BC80BC8)   ; SDRAM Config Reg (Non-MCP Version)
xlli_MDMRS_value   EQU   (0x00320032)   ; SDRAM Mode Reg Set Config Reg

;
; MEMORY PHYSICAL BASE ADDRESS(S)
;

xlli_SRAM_PHYSICAL_BASE      EQU       (0x5C000000)  ; Physical base address for SRAM
xlli_SDRAM_PHYSICAL_BASE     EQU       (0xA8000000)  ; Physical base address for SDRAM


      END