📄 xlli_lowlev_init.s
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ldr r1, =xlli_CLKREGS_PHYSICAL_BASE ; Get clocks register base address
str r5, [r1, #xlli_CCCR_offset] ; Load the new CCCR value
;CLKCFG will be set by xlli_freq_change
mov pc, lr ; Return to calling routine
ENDFUNC
;**************************************************************************************************
;
; ***********************************************
; ********** **********
; ********** FREQUENCY CHANGE SEQUENCE **********
; ********** **********
; ***********************************************
;
; This subroutine initiates the frequency change sequence and restarts the memory controller
;
xlli_freq_change FUNCTION
ldr r2, =xlli_PLATO_CLKCFG_DATA
orr r2, r2, #2 ; Set the F bit
mcr p14, 0, r2, c6, c0, 0 ; initiate the frequency change sequence
;
; If the clock frequency is chaged, the MDREFR Register must be rewritten, even
; if it's the same value. This will result in a refresh being performed and the
; refresh counter being reset to the reset interval. (Section 13.10.3, pg 13-17 of EAS)
;
ldr r4, =xlli_MEMORY_CONFIG_BASE ; Get memory controller base address
ldr r1, [r4, #xlli_MDREFR_offset] ; Get the current state of MDREFR
str r1, [r4, #xlli_MDREFR_offset] ; Re-write this value
mov pc, lr ; return to calling routine
ENDFUNC
;**************************************************************************************************
;
; ********************************************************
; ********** **********
; ********** INITIALIZE OPERATING SYSTEM TIMERS **********
; ********** **********
; ********************************************************
;
; This code segment initializes the OST count registers to zero, clears the
; status bits in OSSR, and zeroes out the match registers.
;
; After this function is called, the OS timers should be initalized to the
; same state as on HW reset.
;
; The interrupt bit for match register 1 is set for use by timing macros.
;
xlli_ost_init FUNCTION
ldr r2, =xlli_OSTREGS_PHYSICAL_BASE ; get base address for os timer registers
mov r3, #0 ; clear work register
str r3, [r2, #xlli_OSCR0_offset] ; zero out OS Timer Count register
str r3, [r2, #xlli_OWER_offset] ; zero out OS Timer Watchdog Match Enable Register
str r3, [r2, #xlli_OIER_offset] ; zero out OS Timer Interrupt Enable register
str r3, [r2, #xlli_OSSR_offset] ; zero out OS Timer Status register
str r3, [r2, #xlli_OMCR4_offset] ; Zero out Match Control Registers
str r3, [r2, #xlli_OMCR5_offset]
str r3, [r2, #xlli_OMCR6_offset]
str r3, [r2, #xlli_OMCR7_offset]
str r3, [r2, #xlli_OMCR8_offset]
str r3, [r2, #xlli_OMCR9_offset]
str r3, [r2, #xlli_OMCR10_offset]
str r3, [r2, #xlli_OMCR11_offset]
str r3, [r2, #xlli_OSCR0_offset] ; Zero out count register 0
str r3, [r2, #xlli_OSCR4_offset] ; Zero out count register 4 - 11
str r3, [r2, #xlli_OSCR5_offset]
str r3, [r2, #xlli_OSCR6_offset]
str r3, [r2, #xlli_OSCR7_offset]
str r3, [r2, #xlli_OSCR8_offset]
str r3, [r2, #xlli_OSCR9_offset]
str r3, [r2, #xlli_OSCR10_offset]
str r3, [r2, #xlli_OSCR11_offset]
str r3, [r2, #xlli_OSMR0_offset] ; zero-out all 12 match registers
str r3, [r2, #xlli_OSMR1_offset]
str r3, [r2, #xlli_OSMR2_offset]
str r3, [r2, #xlli_OSMR3_offset]
str r3, [r2, #xlli_OSMR4_offset]
str r3, [r2, #xlli_OSMR5_offset]
str r3, [r2, #xlli_OSMR6_offset]
str r3, [r2, #xlli_OSMR7_offset]
str r3, [r2, #xlli_OSMR8_offset]
str r3, [r2, #xlli_OSMR9_offset]
str r3, [r2, #xlli_OSMR10_offset]
str r3, [r2, #xlli_OSMR11_offset]
ldr r1, =xlli_OSSR_ALL ; Clear the status bits - these are 'sticky' bits,
str r1, [r2, #xlli_OSSR_offset] ; These bits are cleared by writing 1's to them
mov pc, lr ; return to calling routine
ENDFUNC
;**************************************************************************************************
;
; **************************************************
; ********** **********
; ********** INITIALIZE the POWER MANAGER **********
; ********** **********
; **************************************************
;
; This code initializes the Power Manager
;
xlli_pwrmgr_init FUNCTION
ldr r2, =xlli_PMRCREGS_PHYSICAL_BASE ; get base address of power mgr / reset control regs
mov r1, #0 ; clear a work register
str r1, [r2, #xlli_PWER_offset] ; Reset Power Manager Wake-up register
str r1, [r2, #xlli_PRER_offset] ; Clear Power Manager Rising-Edge Detector Enables
str r1, [r2, #xlli_PFER_offset] ; Clear Power Manager Falling-Edge Detector Enables
str r1, [r2, #xlli_PEDR_offset] ; Clear Power Manager GPIO edge-Detect Status register
str r1, [r2, #xlli_PGSR0_offset] ; Clear GPIO sleep state registers (GPIOs 31:0)
str r1, [r2, #xlli_PGSR1_offset] ; Clear GPIO sleep state registers (GPIOs 63:32)
str r1, [r2, #xlli_PGSR2_offset] ; Clear GPIO sleep state registers (GPIOs 95:64)
str r1, [r2, #xlli_PGSR3_offset] ; Clear GPIO sleep state registers (GPIOs 118:96)
str r1, [r2, #xlli_PSTR_offset] ; Reset Standby Configuration Register
str r1, [r2, #xlli_PVCR_offset] ; Reset Power Manager Voltage Change Control Register
str r1, [r2, #xlli_PKWR_offset] ; Clear Keyboard Wake-up Enable Register
str r1, [r2, #xlli_PKSR_offset] ; Clear Keyboard Edge Detect Status Register
;
; Initialize the PCFR (Power Manager General Congiguration Manager)
;
mov r1, #xlli_PCFR_OPDE ; enable 3.68Mhz power-down
; orr r1, r1, #xlli_PCFR_FP ; enable PCMCIA pin float
; orr r1, r1, #xlli_PCFR_FS ; enable static memory pin float
orr r1, r1, #xlli_PCFR_SYSEN_EN ; System power supply enable pin
str r1, [r2, #xlli_PCFR_offset]
mov pc, lr ; return to calling routine
ENDFUNC
;**************************************************************************************************
;
; ***************************************************************
; ********** **********
; ********** INITIALIZE INTERNAL MEMORY POWER REGISTER **********
; ********** **********
; ***************************************************************
;
; Power up the internal memory for use (Default on system reset)
;
; Note: This subroutine sets the internal memory to the hardware reset default state
; which is all memory in run mode with auto wake-up disabled and never going
; into standby mode.
;
xlli_IMpwr_init FUNCTION
ldr r2, =xlli_IMEMORY_CONFIG_BASE ; get base address of IM Power Management control regs
mov r1, #0 ; Set all memory to RUN mode and disable auto wakeup
str r1, [r2, #xlli_IMPMCR_offset] ; Write the data to the control register
mov pc, lr ; return to calling routine
ENDFUNC
;**************************************************************************************************
;
; ******************************************************
; ********** **********
; ********** SET SDRAM MEMORY BUFFER STRENGTH **********
; ********** ( C Program callable version) **********
; ******************************************************
;
; This subroutine is a "C" callable function that adjusts the buffer drive impedance for SDRAM
;
; REQUIRED PARAMETER:
;
; r0 = buffer strength (Range of 0x0 to 0xF)
;
; Default value is 0x5 on system boot. A higher value results in a lower
; buffer impedance. This subroutine only changes buffer impedance that
; affect SDRAM. See Developer's Manual (Memory Controller) for more details.
;
xlli_setBufImpedance FUNCTION
stmfd sp!, {r1, r2, lr} ; Save r1, r2 and link register on the stack
ldr r1, =xlli_MEMORY_CONFIG_BASE ; Get memory controller base address
;
; Duplicate the value in lowest nibble so it is duplicated in all 8 nibbels
;
and r0, r0, #0xF ; Isolate bits 3:0 of parameter
mov r2, r0, LSL #4 ; Shift 4 bits to the left
orr r0, r0, r2 ; Copy in next significant nibble
mov r2, r2, LSL #4 ; Shift 4 bits to the left
orr r0, r0, r2 ; Copy in next significant nibble
mov r2, r2, LSL #4 ; Shift 4 bits to the left
orr r0, r0, r2 ; Copy in next significant nibble
mov r2, r2, LSL #4 ; Shift 4 bits to the left
orr r0, r0, r2 ; Copy in next significant nibble
mov r2, r2, LSL #4 ; Shift 4 bits to the left
orr r0, r0, r2 ; Copy in next significant nibble
mov r2, r2, LSL #4 ; Shift 4 bits to the left
orr r0, r0, r2 ; Copy in next significant nibble
mov r2, r2, LSL #4 ; Shift 4 bits to the left
orr r0, r0, r2 ; Copy in next significant nibble
;
; The 8 nibbles in r0 are now all the same value
;
str r0, [r1, #xlli_BSCNTR3_offset] ; Set buffer strength for address lines
str r0, [r1, #xlli_BSCNTR0_offset] ; Set buffer strength for SDCLK
ldr r2, [r1, #xlli_BSCNTR1_offset] ; Get buffer strength for BSCNTR1
and r2, r2, #0xF0 ; Preserve bits 7:4 in r2
bic r0, r0, #0xF0 ; Clear bits 7:4 in r0
orr r2, r0, r2 ; OR with the value from BSCNTR1
str r2, [r1, #xlli_BSCNTR1_offset] ; Write buffer strength to BSCNTR1
str r0, [r1, #xlli_BSCNTR2_offset] ; Write buffer strength to BSCNTR2
ldmfd sp!, {r1, r2, pc} ; Restore r1, r2 and return to caller
ENDFUNC
;**************************************************************************************************
;
; ******************************************************
; ********** **********
; ********** SET SDRAM MEMORY BUFFER STRENGTH **********
; ********** (ROM based version) **********
; ******************************************************
;
; This subroutine adjusts the buffer drive impedance for SDRAM
;
; REQUIRED PARAMETER:
;
; r3 = buffer strength (Range of 0x0 to 0xF)
;
; Default value is 0x5 on system boot. A higher value results in a lower
; buffer impedance. This subroutine only changes buffer impedance that
; affect SDRAM. See Developer's Manual (Memory Controller) for more details.
;
xlli_setBufImp FUNCTION
ldr r1, =xlli_MEMORY_CONFIG_BASE ; Get memory controller base address
;
; Duplicate the value in lowest nibble so it is duplicated in all 8 nibbels
;
and r3, r3, #0xF ; Isolate bits 3:0 of parameter
mov r2, r3 ; Copy into r2
mov r2, r2, LSL #4 ; Shift 4 bits to the left
orr r2, r3, r2 ; Copy in next significant nibble
mov r2, r2, LSL #4 ; Shift 4 bits to the left
orr r2, r3, r2 ; Copy in next significant nibble
mov r2, r2, LSL #4 ; Shift 4 bits to the left
orr r2, r3, r2 ; Copy in next significant nibble
mov r2, r2, LSL #4 ; Shift 4 bits to the left
orr r2, r3, r2 ; Copy in next significant nibble
mov r2, r2, LSL #4 ; Shift 4 bits to the left
orr r2, r3, r2 ; Copy in next significant nibble
mov r2, r2, LSL #4 ; Shift 4 bits to the left
orr r2, r3, r2 ; Copy in next significant nibble
mov r2, r2, LSL #4 ; Shift 4 bits to the left
orr r2, r3, r2 ; Copy in next significant nibble
;
; The 8 nibbles in r2 are now all the same value
;
str r2, [r1, #xlli_BSCNTR3_offset] ; Set buffer strength for address lines
str r2, [r1, #xlli_BSCNTR0_offset] ; Set buffer strength for SDCLK
ldr r3, [r1, #xlli_BSCNTR1_offset] ; Get buffer strength for BSCNTR1
and r3, r3, #0xF0 ; Preserve bits 7:4 in r3
bic r2, r2, #0xF0 ; Clear bits 7:4 in r2
orr r3, r3, r2 ; OR with the value from BSCNTR1
str r3, [r1, #xlli_BSCNTR1_offset] ; Write buffer strength to BSCNTR1
str r2, [r1, #xlli_BSCNTR2_offset] ; Write buffer strength to BSCNTR2
mov pc, lr ; Return to calling routine
ENDFUNC
END
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