xlli_lowlev_init.s

Windows CE 6.0 BSP for VOIP sample phone. Intel PXA270 platform.

;
; Copyright (c) Microsoft Corporation.  All rights reserved.
;
;
; Use of this sample source code is subject to the terms of the Microsoft
; license agreement under which you licensed this sample source code. If
; you did not accept the terms of the license agreement, you are not
; authorized to use this sample source code. For the terms of the license,
; please see the license agreement between you and Microsoft or, if applicable,
; see the LICENSE.RTF on your install media or the root of your tools installation.
; THE SAMPLE SOURCE CODE IS PROVIDED "AS IS", WITH NO WARRANTIES OR INDEMNITIES.
;
;
; Copyright 2002-2003 Intel Corporation All Rights Reserved.
;
; Portions of the source code contained or described herein and all documents
; related to such source code (Material) are owned by Intel Corporation
; or its suppliers or licensors and is licensed by Microsoft Corporation for distribution.  
; Title to the Material remains with Intel Corporation or its suppliers and licensors. 
; Use of the Materials is subject to the terms of the Microsoft license agreement which accompanied the Materials. 
; No other license under any patent, copyright, trade secret or other intellectual
; property right is granted to or conferred upon you by disclosure or
; delivery of the Materials, either expressly, by implication, inducement,
; estoppel or otherwise 
; Some portion of the Materials may be copyrighted by Microsoft Corporation.
;
;
;*********************************************************************************
;
;  FILENAME:       Plato_LowLev_Init.s
;
;  PURPOSE:        Provides low Level init procedures written specifically for
;                  the Bulverde/Plato platform.
;
;
;  LAST MODIFIED:  13-Oct-2003
;******************************************************************************
;
; The functions in this source code are called via a branch with link instruction.
; Unless otherwise specified, no system stack is assumed and no registers are preserved.
;
; NOTES:
;
; The use of these subroutines and/or the order in which they are called is, for the most part,
; arbitrary and is left up to the user. Only a few subroutines must be called in a specific order.
; For example, it makes no sense to go to virtual mode before the MMU is initialized and
; the page table is set up.... and, in order to set up the page table, memory needs to be initialized
; first.
;
        INCLUDE  xlli_Bulverde_defs.inc                 ; Bulverde specific include file
        INCLUDE  xlli_Plato_defs.inc                     ; Plato specific include file
;
        AREA    |text|, CODE, READONLY, ALIGN=5         ; Align =5 required for "ALIGN 32" feature to work.
;
; List of Low Level Init functions in this source code include:
;
        EXPORT xlli_GPIO_init             ; Get SCR and LCDCR data and Initialize the GPIO ports
        EXPORT xlli_mem_restart           ; Restart memory controller
        EXPORT xlli_intr_init             ; Interrupt initialization (masks all interrupts)
        EXPORT xlli_freq_change           ; Frequency change sequence
        EXPORT xlli_ost_init              ; Initalize Operating System Timers
        EXPORT xlli_pwrmgr_init           ; Initialize the Power Manager
        EXPORT xlli_IMpwr_init            ; Initialize Internal Memory for use
        EXPORT xlli_setClocks             ; Reads platform switchs and sets Bulverde frequencies
        EXPORT xlli_setBufImpedance       ; Sets SDRAM buffer impedance (C callable)
        EXPORT xlli_setBufImp             ; Sets SDRAM buffer impedance (ROM callable)

        LTORG

;******************************************************************************
;
;
;       ******************
;       *                *
;       * xlli_GPIO_init * Subroutine
;       *                *
;       ******************
;
; This subroutine sets up the GPIO pins in accordance with the values contained in the platform include file.
;
; NOTES: Written for the Bulverde Processor on the Mainstone Development Platform.
;

xlli_GPIO_init   FUNCTION
;
;
;
;
;       Get GPIO registers base address and configure all GPIO lines.
;
        ldr     r0,  =xlli_GPIOREGS_PHYSICAL_BASE   ; Load the GPIO register block base address

        ldr     r1,  =xlli_GPSR0_value              ; Get the pin set values for GPSR0
        str     r1,  [r0, #xlli_GPSR0_offset]       ; Write the R0 values

        ldr     r2,  =xlli_GPSR1_value              ; Get the pin set values for GPSR1
        str     r2,  [r0, #xlli_GPSR1_offset]       ; Write the R1 values

        ldr     r1,  =xlli_GPSR2_value              ; Get the pin set values for GPSR2
        str     r1,  [r0, #xlli_GPSR2_offset]       ; Write the R2 values

        ldr     r2,  =xlli_GPSR3_value              ; Get the pin set values for GPSR3
        str     r2,  [r0, #xlli_GPSR3_offset]       ; Write the R3 values

        ldr     r1,  =xlli_GPCR0_value              ; Get the pin clear values for GPCR0
        str     r1,  [r0, #xlli_GPCR0_offset]       ; Write the R0 values

        ldr     r2,  =xlli_GPCR1_value              ; Get the pin clear values for GPCR1
        str     r2,  [r0, #xlli_GPCR1_offset]       ; Write the R1 values

        ldr     r1,  =xlli_GPCR2_value              ; Get the pin clear values for GPCR2
        str     r1,  [r0, #xlli_GPCR2_offset]       ; Write the R2 values

        ldr     r2,  =xlli_GPCR3_value              ; Get the pin clear values for GPCR3
        str     r2,  [r0, #xlli_GPCR3_offset]       ; Write the R3 values

        ldr     r1,  =xlli_GPDR0_value              ; Get the pin direction values for GPDR0
        str     r1,  [r0, #xlli_GPDR0_offset]       ; Write the R0 values

        ldr     r2,  =xlli_GPDR1_value              ; Get the pin direction values for GPDR1
        str     r2,  [r0, #xlli_GPDR1_offset]       ; Write the R1 values

        ldr     r1,  =xlli_GPDR2_value              ; Get the pin direction values for GPDR2
        str     r1,  [r0, #xlli_GPDR2_offset]       ; Write the R2 values

        ldr     r2,  =xlli_GPDR3_value              ; Get the pin direction values for GPDR3
        str     r2,  [r0, #xlli_GPDR3_offset]       ; Write the R3 values

        ldr     r1,  =xlli_GAFR0_L_value            ; Get the pin alt function values for GAFR0_L
        str     r1,  [r0, #xlli_GAFR0_L_offset]     ; Write the R0_L values

        ldr     r2,  =xlli_GAFR0_U_value            ; Get the pin alt function values for GAFR0_U
        str     r2,  [r0, #xlli_GAFR0_U_offset]     ; Write the R0_U values

        ldr     r1,  =xlli_GAFR1_L_value            ; Get the pin alt function values for GAFR1_L
        str     r1,  [r0, #xlli_GAFR1_L_offset]     ; Write the R1_L values

        ldr     r2,  =xlli_GAFR1_U_value            ; Get the pin alt function values for GAFR1_U
        str     r2,  [r0, #xlli_GAFR1_U_offset]     ; Write the R1_U values

        ldr     r1,  =xlli_GAFR2_L_value            ; Get the pin alt function values for GAFR2_L
        str     r1,  [r0, #xlli_GAFR2_L_offset]     ; Write the R2_L values

        ldr     r2,  =xlli_GAFR2_U_value            ; Get the pin alt function values for GAFR2_U
        str     r2,  [r0, #xlli_GAFR2_U_offset]     ; Write the R2_U values

        ldr     r1,  =xlli_GAFR3_L_value            ; Get the pin alt function values for GAFR3_L
        str     r1,  [r0, #xlli_GAFR3_L_offset]     ; Write the R3_L values

        ldr     r2,  =xlli_GAFR3_U_value            ; Get the pin alt function values for GAFR3_U
        str     r2,  [r0, #xlli_GAFR3_U_offset]     ; Write the R3_U values
;
;       The RDH and PH bits on Bulverde must be set to enable updated GPIO pins.
;       These are sticky bits.
;
        ldr     r0, =xlli_PMRCREGS_PHYSICAL_BASE
        mov     r2, #(xlli_PSSR_PH | xlli_PSSR_RDH) ; Set the PH and RDH bits to enable all GPIOs
        str     r2, [r0, #xlli_PSSR_offset]         ; Enable all GPIO lines

;       Enable GPIO reset on Plato
;
        ldr     r2,  [r0, #xlli_PCFR_offset]        ; Fetch starting value of PCFR
        orr     r2, r2, #xlli_PCFR_GPR_EN           ; Enable GPIO reset
        str     r2, [r0, #xlli_PCFR_offset]         ; Write back value of PCFR
        
        mov     r1, #0x600
xlli_g  subs    r1, r1, #1
        bne     xlli_g

        mov     pc, lr                              ; Return to calling program

        ENDFUNC

        LTORG


;**************************************************************************************************
;
; ***********************************************
; **********                           **********
; ********** RESTART MEMORY CONTROLLER **********
; **********                           **********
; ***********************************************
;
; This command restarts the memory controller and should be called after a frequency change sequence
; or when memory controller settings have been changed (such as xlli_mem_Tmax and xlli_memTopt).
;

xlli_mem_restart   FUNCTION

        ldr     r4,  =xlli_MEMORY_CONFIG_BASE    ; Get memory controller base address
        ldr     r2,  [r4, #xlli_MDREFR_offset]   ; Get MDREFR value
        bic     r3,  r2, #xlli_MDREFR_E0PIN      ; Clear E0PIN to disable SDCKE[0]
        bic     r3,  r3, #xlli_MDREFR_E1PIN      ; Clear E1PIN to disable SDCKE[1]
        b       xlli_5A
;
;       The next line should start on a cache line boundary so we don't accidently hang the system
;
        ALIGN   32
xlli_5A str     r3,  [r4, #xlli_MDREFR_offset]   ; Write value back with E0PIN and E1PIN cleared
        str     r2,  [r4, #xlli_MDREFR_offset]   ; Write value back with E0PIN and E1PIN set
;
; Disable all SDRAM banks
;
        ldr     r1, [r4, #xlli_MDCNFG_offset]    ; Fetch platform value for MDCNFG
        bic     r1, r1,  #(xlli_MDCNFG_DE0 :OR: xlli_MDCNFG_DE1)   ; Disable all
        bic     r1, r1,  #(xlli_MDCNFG_DE2 :OR: xlli_MDCNFG_DE3)   ; SDRAM banks
        str     r1, [r4, #xlli_MDCNFG_offset]   ; Write w/o enabling SDRAM banks
;
; Access memory *not yet enabled* for CBR refresh cycles (8)
; - CBR is generated for all banks
;
        ldr     r1, =xlli_SDRAM_PHYSICAL_BASE
        str     r1, [r1]
        str     r1, [r1]
        str     r1, [r1]
        str     r1, [r1]
        str     r1, [r1]
        str     r1, [r1]
        str     r1, [r1]
        str     r1, [r1]

        str     r1, [r1]  ;  Fix for erratum #116. Makes up for ineffective 1st mem access.
                          ;  This is being left in for Bulverde for the moment
;
; Re-enable SDRAM partition(s)
;
        ldr     r2,  [r4, #xlli_MDCNFG_offset]   ; Fetch the current MDCNFG value
        bic     r2,  r2,  #xlli_MDCNFG_DE0       ; Disable SDRAM bank 0
        bic     r2,  r2,  #xlli_MDCNFG_DE1       ; Disable SDRAM bank 1
        orr     r2,  r2,  #xlli_MDCNFG_DE2       ; Enable SDRAM bank 2 (only bank2 is used)
        bic     r2,  r2,  #xlli_MDCNFG_DE3       ; Disable SDRAM bank 3

        str     r2,  [r4, #xlli_MDCNFG_offset]   ; Write back MDCNFG, enabling the SDRAM bank(s)
;
; Write the MDMRS register to trigger an MRS command to all enabled banks of SDRAM.
;
;
        ldr     r1,  [r4, #xlli_MDMRS_offset]    ; Fetch platform MDMRS value
        str     r1,  [r4, #xlli_MDMRS_offset]    ; Write the MDMRS value back
;
        ldr     r3,  [r4, #xlli_MDREFR_offset]   ; Get MDREFR value
        str     r3,  [r4, #xlli_MDREFR_offset]   ; Write value back

        mov     pc,  lr                         ; return to calling routine
        ENDFUNC


;**************************************************************************************************
;
; ******************************************************
; **********                                  **********
; ********** INITIALIZE (MASK) ALL INTERRUPTS **********
; **********                                  **********
; ******************************************************
;
; NOTE: On system reset, all interrupts should be cleared by hardware.
;       This enforces disabling of all interrupts to HW boot default conditions.
;
xlli_intr_init   FUNCTION

        ldr     r4,  =xlli_INTERREGS_PHYSICAL_BASE  ; Load controller physical base address
        ldr     r2,  =0x0                           ; zero out a work register
        str     r2,  [r4, #xlli_ICMR_offset]        ; Mask all interrupts (clear mask register)
        str     r2,  [r4, #xlli_ICMR2_offset]       ; Mask all interrupts (clear mask register) 2
        str     r2,  [r4, #xlli_ICLR_offset]        ; Clear the interrupt level register
        str     r2,  [r4, #xlli_ICLR2_offset]       ; Clear the interrupt level register 2
        str     r2,  [r4, #xlli_ICCR_offset]        ; Clear Interrupt Control Register
        str     r2,  [r4, #xlli_ICCR2_offset]       ; Clear Interrupt Control Register 2
        mov     pc,  lr                             ; return to calling routine

        ENDFUNC
        

;**************************************************************************************************
;
; ************************************************************
; **********                                        **********
; ********** SET SYSTEM CLOCKS     **********
; **********                                        **********
; ************************************************************
;
; This subroutine sets the Bulverde/Mainstone clocks based on the Mainstone platform switch settings
; NOTE: This subroutine just sets the bits according to switch settings. The user needs to call the
;       change frequency sequence subroutine (xlli_freq_change) for the values to take effect.
;
xlli_setClocks  FUNCTION

        ; Set oscillator configuration register
        ; OSCC = OON | TOUT
        ldr     r1, =xlli_CLKREGS_PHYSICAL_BASE 
        mov     r2, #(xlli_OSCC_OON :OR: xlli_OSCC_TOUT_EN)
        str     r2, [r1, #xlli_OSCC_offset]

        ldr    r5,  =xlli_PLATO_CLK_DATA             ; Get platform register base address