aecdrv.h

Windows CE 6.0 BSP for VOIP sample phone. Intel PXA270 platform.

//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this sample source code is subject to the terms of the Microsoft
// license agreement under which you licensed this sample source code. If
// you did not accept the terms of the license agreement, you are not
// authorized to use this sample source code. For the terms of the license,
// please see the license agreement between you and Microsoft or, if applicable,
// see the LICENSE.RTF on your install media or the root of your tools installation.
// THE SAMPLE SOURCE CODE IS PROVIDED "AS IS", WITH NO WARRANTIES OR INDEMNITIES.
//
/*++
THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
PARTICULAR PURPOSE.

Module Name:  

  ssplink.h

Abstract:  

Notes:

Revision History:

--*/

#ifndef __AECAUDIODRV_H__
#define __AECAUDIODRV_H__

#ifdef __cplusplus
extern "C"{
#endif 

typedef struct
{
    unsigned int sscr0;         // 0x.... 0000
    unsigned int sscr1;         // 0x.... 0004
    unsigned int sssr;          // 0x.... 0008
    unsigned int ssitr;         // 0x.... 000C
    unsigned int ssdr;          // 0x.... 0010
    unsigned int rsvd1[5];      // 0x.... 0014
    unsigned int ssto;          // 0x.... 0028
    unsigned int sspsp;         // 0x.... 002C
    unsigned int sstsa;         // 0x.... 0030
    unsigned int ssrsa;         // 0x.... 0034
    unsigned int sstss;         // 0x.... 0038
    unsigned int ssacd;         // 0x.... 003C
} XLLP_SSPREGS_T , *P_XLLP_SSPREGS_T;

BOOL AecAudioInit();
BOOL DeAecAudioInit();
BOOL PowerUpAEC();
BOOL PowerDownAEC();
BOOL AEC_SSPLinkSetup();
BOOL AEC_SSPLinkGpioConfigure(volatile P_XLLP_GPIO_T v_pGPIORegs);
void AEC_SSPLinkInit();
BOOL AEC_SSPLinkWrite(unsigned char start, unsigned int data);
BOOL AEC_SSPLinkRead(unsigned char start, unsigned int *data);
static BOOL AllocateAECResources();

//SSP2 Clock 
#define CLK_SSP2 0x00000008

// SSP Control Regsiter 0 (SSCR0_1/2/3)
#define SSCR0_MOD                           0x80000000
#define SSCR0_ACS                           0x40000000
#define SSCR0_FRDC(n)                       ((n) << 24)
#define SSCR0_TIM                           0x00800000
#define SSCR0_RIM                           0x00400000
#define SSCR0_NCS                           0x00200000
#define SSCR0_EDSS                          0x00100000
#define SSCR0_SCR(n)                        (n << 8)
#define SSCR0_SSE                           0x00000080
#define SSCR0_ECS                           0x00000040
#define SSCR0_FRF(n)                        ((n) << 4)
#define SSCR0_DSS(n)                        (n)

#define SSCR0_DSS_FRF_SPI                   0x0
#define SSCR0_DSS_FRF_SSP                   0x1
#define SSCR0_DSS_FRF_MWI                   0x2


// SSP Control Register 1 (SSCR1_1/2/3)
#define SSCR1_TTELP                         0x80000000
#define SSCR1_TTE                           0x40000000
#define SSCR1_EBCEI                         0x20000000
#define SSCR1_SCFR                          0x10000000
#define SSCR1_ECRA                          0x08000000
#define SSCR1_ECRB                          0x04000000
#define SSCR1_SCLKDIR                       0x02000000
#define SSCR1_SFRMDIR                       0x01000000
#define SSCR1_RWOT                          0x00800000
#define SSCR1_TRAIL                         0x00400000
#define SSCR1_TSRE                          0x00200000
#define SSCR1_RSRE                          0x00100000
#define SSCR1_TINTE                         0x00080000
#define SSCR1_PINTE                         0x00040000
#define SSCR1_IFS                           0x00010000
#define SSCR1_STRF                          0x00008000
#define SSCR1_EFWR                          0x00004000
#define SSCR1_RFT(n)                        ((n) << 10)
#define SSCR1_TFT(n)                        ((n) << 6)
#define SSCR1_MWDS                          0x00000020
#define SSCR1_SPH                           0x00000010
#define SSCR1_SPO                           0x00000008
#define SSCR1_LBM                           0x00000004
#define SSCR1_TIE                           0x00000002
#define SSCR1_RIE                           0x00000001

// SSP Status Register (SSSR_1/2/3)
#define SSSR_BCE                            0x00800000
#define SSSR_CSS                            0x00400000
#define SSSR_TUR                            0x00200000
#define SSSR_EOC                            0x00100000
#define SSSR_TINT                           0x00080000
#define SSCR_PINT                           0x00040000
#define SSCR_RFL(n)                         ((n) << 12)
#define SSCR_TFL(n)                         ((n) << 8)
#define SSCR_ROR                            0x00000080
#define SSCR_RFS                            0x00000040
#define SSCR_TFS                            0x00000020
#define SSCR_BSY                            0x00000010
#define SSCR_RNE                            0x00000008
#define SSCR_TNF                            0x00000004

// Redundant, but more readable
#define SSP_RECEIVE_FIFO_NOT_EMPTY          0x8
#define SSP_TRANSMIT_FIFO_NOT_FULL          0x4



//Define AEC chipset Registers
#define AEC_CR0   0x00
#define AEC_CR1   0x01
#define AEC_CR2   0x02
#define AEC_CR3   0x03
#define AEC_CR4   0x04
#define AEC_CR5   0x05
#define AEC_CR6   0x06
#define AEC_CR7   0x07
#define AEC_CR8   0x08
#define AEC_CR9   0x09
#define AEC_CR10  0x0A
#define AEC_CR11  0x0B
#define AEC_CR12  0x0C





#ifdef __cplusplus
}
#endif 

#endif __AECAUDIODRV_H__