📄 display.c
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//
// Copyright (c) Microsoft Corporation. All rights reserved.
//
//
// Use of this sample source code is subject to the terms of the Microsoft
// license agreement under which you licensed this sample source code. If
// you did not accept the terms of the license agreement, you are not
// authorized to use this sample source code. For the terms of the license,
// please see the license agreement between you and Microsoft or, if applicable,
// see the LICENSE.RTF on your install media or the root of your tools installation.
// THE SAMPLE SOURCE CODE IS PROVIDED "AS IS", WITH NO WARRANTIES OR INDEMNITIES.
//
//------------------------------------------------------------------------------
//
// File: display.c
//
// Basic LCD driver for bootloader, derived from the display driver init code
// found in src\drivers\display\dispdr.c.
//
// With the supplied 8x18 font, the display is 30 characters wide by 17 lines high.
// This is currently set up as a 12 line fixed menu (lines 0-11) and 5 line (12-16)
// scrolling area.
#include <windows.h>
#include <bsp.h>
#include <ceddk.h>
#include <blcommon.h>
#include <oal_memory.h>
#include <bulverde_base_regs.h>
#include <xllp_gpio.h>
#include <xllp_defs.h>
#include <xllp_lcd.h>
#include <xllp_ost.h>
#include <dispCtrlrData.h>
#include <ssplink.h>
#include "loader.h"
#include "wait.h"
#include "font.h"
//------------------------------------------------------------------------------
// External function prorotypes.
//
BOOL DisplaySplashScreen(UINT16 * fb);
BOOL OEMReportError(DWORD dwReason, DWORD dwReserved);
//------------------------------------------------------------------------------
// Global variables.
//
extern BSP_ARGS *g_pBSPArgs;
extern EBOOT_CFG g_EbootCFG;
extern BOOL g_DownloadImage;
extern BOOL g_FormatFlash;
BOOL g_DisplayMenu;
volatile XLLP_SSPREGS_T *g_pSSPRegs=NULL;
// Use the same framebuffer start address as the CE driver.
#define g_pBLFrameBufferPhysical (INTERNAL_MEMORY_START + (4 * 0x20) + 0x400)
#define RGBU16(r,g,b) ((UINT16)((r>>3)<<11 | (g>>2)<<5 | (b>>3)))
#define xstr(s) str(s)
#define str(s) #s
void InitLCDController()
{
int i = 0;
int BPP = 0;
int PCD = 0;
int LCLK = 0;
unsigned int CCCR_L = 0;
PBYTE gFrameBuffer;
volatile LCDRegs *p_LCDRegs;
volatile XLLP_CLKMGR_T *p_CLKRegs;
volatile XLLP_SSPREGS_T *p_SSPRegs;
volatile XLLP_GPIO_T *p_GPIORegs;
volatile XLLP_OST_T *p_OSTRegs;
LCD_FRAME_DESCRIPTOR *frameDescriptorCh0fd1 = (LCD_FRAME_DESCRIPTOR *) OALPAtoVA(INTERNAL_MEMORY_START, FALSE);
gFrameBuffer = (UINT8 *)OALPAtoVA(g_pBLFrameBufferPhysical, FALSE);
if (gFrameBuffer == 0 || frameDescriptorCh0fd1 == 0)
{
KITLOutputDebugString("LCDInitController: bad memory\r\n");
return;
}
p_LCDRegs = (volatile LCDRegs *) OALPAtoVA(BULVERDE_BASE_REG_PA_LCD, FALSE);
p_CLKRegs = (volatile XLLP_CLKMGR_T *) OALPAtoVA(BULVERDE_BASE_REG_PA_CLKMGR, FALSE);
p_GPIORegs = (volatile XLLP_GPIO_T *) OALPAtoVA(BULVERDE_BASE_REG_PA_GPIO, FALSE);
p_OSTRegs = (volatile XLLP_OST_T *) OALPAtoVA(BULVERDE_BASE_REG_PA_OST, FALSE);
p_SSPRegs = (volatile XLLP_SSPREGS_T *) OALPAtoVA(BULVERDE_BASE_REG_PA_SSP3, FALSE);
p_LCDRegs->LCCR0 = 0;
p_LCDRegs->LCCR1 = 0;
p_LCDRegs->LCCR2 = 0;
p_LCDRegs->LCCR3 = 0;
p_LCDRegs->LCCR4 = 0;
p_LCDRegs->LCCR5 = (LCD_SOFM1|LCD_SOFM2|LCD_SOFM3|LCD_SOFM4|LCD_SOFM5|LCD_SOFM6|
LCD_EOFM1|LCD_EOFM2|LCD_EOFM3|LCD_EOFM4|LCD_EOFM5|LCD_EOFM6|
LCD_BSM1 |LCD_BSM2 |LCD_BSM3 |LCD_BSM4 |LCD_BSM5 |LCD_BSM6 |
LCD_IUM1 |LCD_IUM2 |LCD_IUM3 |LCD_IUM4 |LCD_IUM5 |LCD_IUM6 );
// Enable the LCD and SRAM clocks
p_CLKRegs->cken = (p_CLKRegs->cken & XLLP_CLKEN_MASK) | CLK_LCD | CLK_SRAM;
// Configure the general purpose frame descriptor
//
// Set the physical address of the frame descriptor
frameDescriptorCh0fd1->FDADR = LCD_FDADR(INTERNAL_MEMORY_START);
// Set the physical address of the frame buffer
frameDescriptorCh0fd1->FSADR = LCD_FSADR(g_pBLFrameBufferPhysical);
// Clear the frame ID
frameDescriptorCh0fd1->FIDR = LCD_FIDR(0);
// Set the DMA transfer length to the size of the frame buffer
frameDescriptorCh0fd1->LDCMD = LCD_Len(320*240*2);
// Load the contents of FDADR0 with the physical address of this frame descriptor
p_LCDRegs->FDADR0 = LCD_FDADR(frameDescriptorCh0fd1->FDADR);
// Determine the LCLK frequency programmed into the CCCR.
// This value will be used to calculate a Pixel Clock Divisor (PCD)
// for a given display type.
CCCR_L = (p_CLKRegs->cccr & 0x0000001F);
if (CCCR_L < 8) // L = [2 - 7]
LCLK = (13 * CCCR_L) * 100;
else if (CCCR_L < 17) // L = [8 - 16]
LCLK = ((13 * CCCR_L) * 100) >> 1;
else if (CCCR_L < 32) // L = [17 - 31]
LCLK = ((13 * CCCR_L) * 100) >> 2;
BPP = 4;
PCD = (LCLK / (2 * HD66781_PIXEL_CLOCK_FREQUENCY));
p_LCDRegs->LCCR0 = (LCD_LDM | LCD_SFM | LCD_IUM | LCD_EFM |
LCD_PAS | LCD_QDM | LCD_BM | LCD_OUM);
p_LCDRegs->LCCR1 = (LCD_PPL(0x0EF) | LCD_HSW(0x01) |
LCD_ELW(0x09) | LCD_BLW(0x09));
p_LCDRegs->LCCR2 = (LCD_LPP(0x13F) | LCD_VSW(0x01) |
LCD_EFW(0x08) | LCD_BFW(0x08));
p_LCDRegs->LCCR3 = (LCD_PCD(PCD) | LCD_BPP(BPP) | LCD_VSP |
LCD_HSP | LCD_OEP);
p_LCDRegs->LCCR4 = LCD_PAL_FOR(0);
}
void SetupLCDGPIOs()
{
volatile XLLP_GPIO_T *p_GPIORegs;
p_GPIORegs = (volatile XLLP_GPIO_T *) OALPAtoVA(BULVERDE_BASE_REG_PA_GPIO, FALSE);
p_GPIORegs->GPDR0 = (p_GPIORegs->GPDR0 & ~XLLP_GPIO_BIT_L_VSYNC) | (XLLP_GPIO_BIT_PWM_OUT0 | XLLP_GPIO_BIT_L_CS);
p_GPIORegs->GPDR1 |= ( XLLP_GPIO_BIT_L_DD0 | XLLP_GPIO_BIT_L_DD1 | XLLP_GPIO_BIT_L_DD2 | XLLP_GPIO_BIT_L_DD3 | XLLP_GPIO_BIT_L_DD4 | XLLP_GPIO_BIT_L_DD5);
p_GPIORegs->GPDR2 |= ( XLLP_GPIO_BIT_L_DD6 | XLLP_GPIO_BIT_L_DD7 | XLLP_GPIO_BIT_L_DD8 | XLLP_GPIO_BIT_L_DD9 | XLLP_GPIO_BIT_L_DD10 |
XLLP_GPIO_BIT_L_DD11 | XLLP_GPIO_BIT_L_DD12 | XLLP_GPIO_BIT_L_DD13 | XLLP_GPIO_BIT_L_DD14 | XLLP_GPIO_BIT_L_DD15 |
XLLP_GPIO_BIT_L_FCLK | XLLP_GPIO_BIT_L_LCLK | XLLP_GPIO_BIT_L_PCLK | XLLP_GPIO_BIT_L_BIAS);
// Program the GAFR0_L to select alternate function 1 for GPIO 14.
p_GPIORegs->GAFR0_L = (p_GPIORegs->GAFR0_L & ~XLLP_GPIO_AF_BIT_L_VSYNC_MASK) | (XLLP_GPIO_AF_BIT_L_VSYNC);
// Program the GAFR0_U to select alternate function 2 for GPIO 19.
p_GPIORegs->GAFR0_U = (p_GPIORegs->GAFR0_U & ~XLLP_GPIO_AF_BIT_L_CS_MASK) | (XLLP_GPIO_AF_BIT_L_CS);
// Program the GAFR1_U to select alternate function 2 for GPIO 58 through 63.
p_GPIORegs->GAFR1_U = (p_GPIORegs->GAFR1_U & ~(XLLP_GPIO_AF_BIT_L_DD0_MASK | XLLP_GPIO_AF_BIT_L_DD1_MASK | XLLP_GPIO_AF_BIT_L_DD2_MASK|
XLLP_GPIO_AF_BIT_L_DD3_MASK | XLLP_GPIO_AF_BIT_L_DD4_MASK | XLLP_GPIO_AF_BIT_L_DD5_MASK)) |
(XLLP_GPIO_AF_BIT_L_DD0 | XLLP_GPIO_AF_BIT_L_DD1 | XLLP_GPIO_AF_BIT_L_DD2 |
XLLP_GPIO_AF_BIT_L_DD3 | XLLP_GPIO_AF_BIT_L_DD4 | XLLP_GPIO_AF_BIT_L_DD5 );
// Program the GAFR2_L to select alternate function 2 for GPIO 64 through 77.
p_GPIORegs->GAFR2_L = (p_GPIORegs->GAFR2_L & ~(XLLP_GPIO_AF_BIT_L_DD6_MASK | XLLP_GPIO_AF_BIT_L_DD7_MASK | XLLP_GPIO_AF_BIT_L_DD8_MASK |
XLLP_GPIO_AF_BIT_L_DD9_MASK | XLLP_GPIO_AF_BIT_L_DD10_MASK | XLLP_GPIO_AF_BIT_L_DD11_MASK |
XLLP_GPIO_AF_BIT_L_DD12_MASK | XLLP_GPIO_AF_BIT_L_DD13_MASK | XLLP_GPIO_AF_BIT_L_DD14_MASK |
XLLP_GPIO_AF_BIT_L_DD15_MASK | XLLP_GPIO_AF_BIT_L_FCLK_RD_MASK | XLLP_GPIO_AF_BIT_L_LCLK_A0_MASK |
XLLP_GPIO_AF_BIT_L_PCLK_WR_MASK | XLLP_GPIO_AF_BIT_L_BIAS_MASK)) |
(XLLP_GPIO_AF_BIT_L_DD6 | XLLP_GPIO_AF_BIT_L_DD7 | XLLP_GPIO_AF_BIT_L_DD8 |
XLLP_GPIO_AF_BIT_L_DD9 | XLLP_GPIO_AF_BIT_L_DD10 | XLLP_GPIO_AF_BIT_L_DD11 |
XLLP_GPIO_AF_BIT_L_DD12 | XLLP_GPIO_AF_BIT_L_DD13 | XLLP_GPIO_AF_BIT_L_DD14 |
XLLP_GPIO_AF_BIT_L_DD15 | XLLP_GPIO_AF_BIT_L_FCLK_RD| XLLP_GPIO_AF_BIT_L_LCLK_A0|
XLLP_GPIO_AF_BIT_L_PCLK_WR | XLLP_GPIO_AF_BIT_L_BIAS );
// Program the GAFR2_U to select alternate function 2 for GPIO 87.
p_GPIORegs->GAFR2_U = p_GPIORegs->GAFR2_U & ~XLLP_GPIO_AF_BIT_L_DD17_MASK;
}
void EnableLCDController()
{
volatile LCDRegs *p_LCDRegs;
volatile XLLP_GPIO_T *p_GPIORegs;
p_LCDRegs = (volatile LCDRegs *) OALPAtoVA(BULVERDE_BASE_REG_PA_LCD, FALSE);
p_GPIORegs = (volatile XLLP_GPIO_T *) OALPAtoVA(BULVERDE_BASE_REG_PA_GPIO, FALSE);
p_LCDRegs->LCCR0 |= LCD_ENB;
// Turn on the backlight
p_GPIORegs->GPSR0 |= XLLP_GPIO_BIT_PWM_OUT0;
}
void ClearLCDStatusReg()
{
volatile LCDRegs *p_LCDRegs;
p_LCDRegs = (volatile LCDRegs *) OALPAtoVA(BULVERDE_BASE_REG_PA_LCD, FALSE);
// Clear the status registers by writing 1's to each bit.
p_LCDRegs->LCSR0 = ( LCD_LDD | LCD_SOF0| LCD_BER | LCD_ABC | LCD_IU0 |
LCD_IU1 | LCD_OU | LCD_QD | LCD_EOF0| LCD_BS0 |
LCD_SINT| LCD_RD_ST | LCD_CMD_INTR );
p_LCDRegs->LCSR1 = ( LCD_SOF1| LCD_SOF2| LCD_SOF3| LCD_SOF4| LCD_SOF5 | LCD_SOF6 |
LCD_EOF1| LCD_EOF2| LCD_EOF3| LCD_EOF4| LCD_EOF5 | LCD_EOF6 |
LCD_BS1 | LCD_BS2 | LCD_BS3 | LCD_BS4 | LCD_BS5 | LCD_BS6 |
LCD_IU2 | LCD_IU3 | LCD_IU4 | LCD_IU5 | LCD_IU6 );
}
BOOL SetupSSPLink()
{
volatile XLLP_CLKMGR_T *p_CLKRegs;
volatile XLLP_GPIO_T *p_GPIORegs;
volatile XLLP_SSPREGS_T *p_SSPRegs;
DWORD FIFOCnt,i;
p_CLKRegs = (volatile XLLP_CLKMGR_T *) OALPAtoVA(BULVERDE_BASE_REG_PA_CLKMGR, FALSE);
p_GPIORegs = (volatile XLLP_GPIO_T *) OALPAtoVA(BULVERDE_BASE_REG_PA_GPIO, FALSE);
p_SSPRegs = (volatile XLLP_SSPREGS_T *) OALPAtoVA(BULVERDE_BASE_REG_PA_SSP3, FALSE);
g_pSSPRegs = p_SSPRegs;
// Turn on SSP3 clock
p_CLKRegs->cken = (p_CLKRegs->cken & XLLP_CLKEN_MASK) | CLK_SSP3;
// SSPLinkGpioConfigure
p_GPIORegs->GPDR2 |= 0x001A0000;
p_GPIORegs->GAFR2_U &= ~(0x000003FC);
p_GPIORegs->GAFR2_U |= 0x00000154;
// Sets up the SSP controller to Xmit 16 bit Data to the Renesas, frames are sent in the SPI format
p_SSPRegs->sscr0 = 0x00000000;
p_SSPRegs->sscr0 = SSCR0_TIM | SSCR0_RIM | SSCR0_SCR(0x10) | SSCR0_DSS(7);
p_SSPRegs->sscr1 = SSCR1_SPH | SSCR1_SPO;
p_SSPRegs->sscr0 |= SSCR0_SSE;
msWait(5);
// Flush FIFO
FIFOCnt = 0x10;
for (i=0; i<FIFOCnt; i++)
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