g3_startup.s

Windows CE 6.0 BSP for VOIP sample phone. Intel PXA270 platform.

;
; Copyright (c) Microsoft Corporation.  All rights reserved.
;
;
; Use of this sample source code is subject to the terms of the Microsoft
; license agreement under which you licensed this sample source code. If
; you did not accept the terms of the license agreement, you are not
; authorized to use this sample source code. For the terms of the license,
; please see the license agreement between you and Microsoft or, if applicable,
; see the LICENSE.RTF on your install media or the root of your tools installation.
; THE SAMPLE SOURCE CODE IS PROVIDED "AS IS", WITH NO WARRANTIES OR INDEMNITIES.
;
;
;*********************************************************************************
;  FILENAME:    g3_startup.s
;
;
;  PURPOSE:     Code to read eboot (bootloader) from MDOC G3 chip, copy to
;               SDRAM and jump to it.
;
;  NOTES:       
;******************************************************************************

;===============================================================
; #1 - Define Features
;===============================================================
        GBLL    TEST_MODE
; TEST_MODE               SETL    {TRUE}
TEST_MODE                SETL    {FALSE}
        GBLL    SPL_MODE
SPL_MODE                SETL    {TRUE}      ;Eboot is stored in SPL partition
;SPL_MODE                SETL    {FALSE}    ;Eboot is stored in non-SPL partition

;===============================================================
; #2 - Define your DiskOnChip window 
;===============================================================
MDOCPBaseAddress        EQU     0x00000000  ; MDOC is using CS0 on Plato.

;----- DiskOnChip Millennium Plus registers --------------------
CDSN_IO                 EQU     0x0800 ; CDSN IO Register
CDSN_IO_CORR            EQU     0x02
CDSN_CNTR               EQU     0x1000 ; CDSN Control
MDOCPBaseAddressIO      EQU     MDOCPBaseAddress+CDSN_IO
MDOCPBaseAddressCNTR    EQU     MDOCPBaseAddress+CDSN_CNTR
G3_NNOPreg              EQU     0x3E   ; NOP Register
G3_NDOCcontrol          EQU     0x0C   ; DOC Control Register
G3_NDOCcontrolConfirm   EQU     0x72   ; DOC Control Confirmation Register
G3_NdeviceSelect        EQU     0x0A   ; Flash Select Register
G3_NflashSequence       EQU     0x32   ; Flash Sequence Register
G3_NflashCommand        EQU     0x34   ; Flash Command Register
G3_NflashDataEnd        EQU     0x1E   ; Flash End Data Register
G3_NflashAddress        EQU     0x36   ; Flash Address Register
G3_NflashControl        EQU     0x38   ; Flash Control Register
G3_NECCcontrol_0        EQU     0x40   ; ECC Control Register
G3_NECCcontrol_1        EQU     0x42
G3_NreadAddrReg         EQU     0x1A   ; Read Address Register
;------------ EDC modes ----------------------------------------
G3_EDC_ERROR_MASK       EQU     0x80   ; EDC Error detection
G3_EDC_VAL              EQU     0x8A0F ; EDC Mode for 527 bytes
;----- Flash Commands ------------------------------------------
RESET_FLASH_CMD         EQU     0xFF   ; Reset Flash Command
READ_A_FLASH_CMD        EQU     0x0    ; Read Area A from Flash
READ_C_FLASH_CMD        EQU     0x50   ; Read Area C from Flash
SLC_MODE_CMD            EQU     0xA2   ; SLC mode select Command
RELIABLE_SLC_MODE_CMD   EQU     0x22   ; Reliable SLC mode select Command
AUTO_PAGE_INC_CMD       EQU     0xB3   ; Auto page inc mode select Command
READ_CMD                EQU     0x60   ; Read Command
MULTI_READ_CMD          EQU     0x30   ; Multi Read Command
REGISTER_READ_CMD       EQU     0xE0   ; Register Read Command
ADDR_INPUT_FOR_REG_READ EQU     0x05   ; Addr input for reg read command
G3_PLANE_0              EQU     0x00   ; Plane 0
G3_PLANE_1              EQU     0x40   ; Plane 1
;----- Flash Sequences ------------------------------------------
ResetFlash_Seq          EQU     0      ; Reset Flash Sequence
READ_A_Seq              EQU     14     ; Read Area A from Flash
READ_C_Seq              EQU     16     ; Read Area C from Flash
SLC_MODE_Seq            EQU     9      ; SLC mode select sequence
AUTO_PAGE_INC_Seq       EQU     12     ; Auto page inc mode select sequence
READ_Seq                EQU     18     ; Read Sequence
;------------ Bits for writing to Input_Config -----------------
IPL_MAX_ID              EQU     0x30   ; Set 4 IPL areas active
;------------ Bits for reading CDSN_Conrol_Status --------------
G3_RB_SHIFT             EQU     31
;------------ Bits for writing to CDSN_Conrol_Status -----------
G3_CDSN_CE              EQU     0x39   ; Chip Enable and inhibit programming
;------------ Bits for reading CDSN_Protection_Status ----------
G3_ACCESS_ERR           EQU     0x06   ; Access Error bits
;------------ ASIC modes ---------------------------------------
DOC_CTRL_NORMAL_MODE    EQU     0x05
;------------ Data Define --------------------------------------
TRUE                    EQU     1
FALSE                   EQU     0
BLOCK_DATA              EQU     0x200       ; 512 bytes
DUMMY_DATA              EQU     10
G3_EDC_DATA             EQU     16
G3_PAGE_OFFSET          EQU     0x84
G3_SIGN_OFFSET          EQU     0x80
END_SPL_ADDR            EQU     0x1000/2    ; 2 Mbytes
G3_SPL_NEXT             EQU     0x80        ; 128 * page size
SPL_START               EQU     0x80        ; After special area (0x280)
MDOC32_ID               EQU     0x40
MDOC512_ID              EQU     0x20
G3_PAGES_IN_UNIT        EQU     0x40        ; 64 pages

;===============================================================
; #3 - Define System RAM address for IPL/SPL code
;===============================================================
;IPL_RAM_ADDRESS        EQU     (0xA8000000) ; Plato does not copy MDOCLDR to RAM.
                                             ; It runs MDOCLDR directly (XIP) from FLASH.
SPL_RAM_ADDRESS         EQU     EBOOT_RAM_ADDRESS   ; Address of Eboot in RAM. Plato's SDRAM on
                                                    ; SDCS2 is mapped to Physical address 0xA8000000.
                                                    ; eboot.bib maps the code to 0xA8020000.
                                                    ; This is where eboot will be copied to in RAM.

;===============================================================
; #4 - Define IPL/SPL size to be copied from Flash to RAM
;           - Size in pages of 512 bytes
;===============================================================
;IPL_SIZE           EQU     2048            ; IPL = 2Kb
                                            ; Don't need it as Plato does not copy MDOCLDR to RAM.
SPL_SIZE            EQU     (EBOOT_SIZE/512) ; SPL partition Eboot.
                                             ; if Eboot=256K. SPL_SIZE=512.
                                             ; if Eboot=320K. SPL_SIZE=640
                                             
;===============================================================
; #5 - change SPL signature
;===============================================================
SPL_SIGN                EQU     0x4F504942  ; = BIPO    ;Default is BIPO
;SPL_SIGN                EQU     0x544F4F42  ; = BOOT
;-------------------------------------------------------------------------

;******************************************************************************
;
; FUNCTION: LoadEboot
;
; Entry point into g3_startup.s
;
; Copies Eboot from G3 MDOC chip's SPL partition to SDRAM and jumps to it.
; NOTE: On system reset, all interrupts should be cleared by hardware.
;       This enforces disabling of all interrupts to HW boot default conditions.
;
;******************************************************************************
    ALIGN
LoadEboot

;---------------------------------------------------------------
; 1. Setup destination before copying SPL and Size
;---------------------------------------------------------------
        mov     r11, #SPL_SIZE          ; Get SPL Size
        ldr     r12, =SPL_RAM_ADDRESS   ; Get SPL Address

        ; set DiskOnChip window
        ldr     r1, =MDOCPBaseAddressCNTR

;----- Registers Usage: ----------------------------------------
; r0  - temp0
; r1  - temp1 - CDSN_IO (offset 0x800) and CDSN_CNTR (offset 0x1000)
; r2  - temp2
; r3  - current page pointer (page address)
; r4  - page counter
; r5  - temp3 - offset for CDSN_CNTR
; r6  - functions parameter 1
; r7  - temp4 - functions parameter 2
; r8  - page offset
; r9  - page in unit mask
; r10 - return address
; r11 - SPL Size
; r12 - pointer to SPL in RAM
;---------------------------------------------------------------

;---------------------------------------------------------------
; 3. Load SPL starting address (address is in Flash)
;---------------------------------------------------------------
        mov     r3, #(SPL_START << 2)
        IF SPL_MODE
        mov     r9, #((G3_PAGES_IN_UNIT - 1) >> 1)
        ELSE
        mov     r9, #(G3_PAGES_IN_UNIT - 1)
        ENDIF
        mov     r4, #1

;---------------------------------------------------------------
; 4. Get Asic ready
;---------------------------------------------------------------
        ldrb    r2, [r1, #G3_NDOCcontrol]   ; First Time Access
        mov     r2, #DOC_CTRL_NORMAL_MODE
        strb    r2, [r1, #G3_NDOCcontrol]
        mvn     r2, r2                      ; move NOT
        strb    r2, [r1, #G3_NDOCcontrolConfirm]
        strh    r1, [r1, #G3_NreadAddrReg]  ; write NchipId addr to addr-reg
        ldrh    r2, [r1]                    ; Read chip ID.
        cmp     r2, #(MDOC512_ID << 4)


        ; Stop if there is no MDOC
        bne     MDOC_NotFound

        strb    r1, [r1, #G3_NdeviceSelect] ; Set Floor 0
        mov     r0, #G3_CDSN_CE             ; set WP | CE
        strb    r0, [r1, #G3_NflashControl]
;---------------------------------------------------------------
; 5. Look for SPL start
;---------------------------------------------------------------
G3_FindNextUnit
        ; Clean Access Error
        mov     r7, #ResetFlash_Seq         ; Reset Sequence
        mov     r6, #RESET_FLASH_CMD        ; Reset Command
        bl      G3_SendCommandAndSeq
        bl      G3_WaitForReady
        strb    r0, [r1, #G3_NNOPreg]       ; NOP

        ; Set SLC Mode
        IF SPL_MODE
        mov     r7, #SLC_MODE_Seq           ; SLC Mode Sequence
        mov     r6, #SLC_MODE_CMD           ; SLC Mode Command
        bl      G3_SendCommandAndSeq
        mov     r6, #RELIABLE_SLC_MODE_CMD
        bl      G3_SendCommand
        ENDIF ; SPL_MODE

G3_continue_search
        add     r3, r3, #G3_SPL_NEXT

        ; Read Signature
        bl      G3_ReadCommandInit

        ; Check For Protection Error
        add     r7, r1, #G3_NflashControl
        strh    r7, [r1, #G3_NreadAddrReg]
        ldrb    r0, [r7]
        tst     r0, #G3_ACCESS_ERR
        bne     G3_FindNextUnit ; skip unit in case of protection violation

        ; Set Signatue Offset
        mov     r8, #G3_SIGN_OFFSET
        bl      G3_ReadCommandContinue
        ldr     r6, =SPL_SIGN