hwinit.s

Windows CE 6.0 BSP for VOIP sample phone. Intel PXA270 platform.

    ldr     r2,  =xlli_MCIO1_value          ; write MCIO1
    str     r2,  [r4, #xlli_MCIO1_offset]

    ;
    ;  STEP 1 - 3rd bullet: Write FLYCNFG
    ;  *******************
    ;
    ldr     r1,  =xlli_FLYCNFG_value        ; write FLYCNFG
    str     r1,  [r4, #xlli_FLYCNFG_offset]

    ;
    ;  STEP 1 - 4th bullet: SKIPPED (used only when coming out of sleep)
    ;  *******************
    ;
    ;     (If required, this would be a write to MDCNFG with enable bits deasserted.)


    ;
    ;  STEP 1 - 5th bullet: update MDREFR settings
    ;  *******************
    ;
    ldr     r2,  =xlli_MDREFR_value            ; Fetch MDREFR value for this platform

    orr     r2,  r2, #xlli_MDREFR_K0RUN    ; Enable RUNs
    orr     r2,  r2, #xlli_MDREFR_K1RUN    ; Enable RUNs
    orr     r2,  r2, #xlli_MDREFR_K2RUN    ; Enable RUNs

    ; configure divisors
    orr     r2,  r2, #xlli_MDREFR_K0DB2     
    bic     r2,  r2, #xlli_MDREFR_K0DB4 
    orr     r2,  r2, #xlli_MDREFR_K1DB2 
    bic     r2,  r2, #xlli_MDREFR_K2DB2 

    ; configure free run bits
    bic     r2,  r2, #(xlli_MDREFR_K0FREE :OR: xlli_MDREFR_K1FREE :OR: xlli_MDREFR_K2FREE)

    orr     r2, r2, #xlli_MDREFR_E1PIN      ; Assert E1PIN to enable SDCKE

    str     r2,  [r4, #xlli_MDREFR_offset] ; Write back MDREFR
    ldr     r2, [r4, #xlli_MDREFR_offset]   ; read back
    nop                                     ; Do not remove!
    nop                                     ; Do not remove!


    ; ***** STEP 2 *****
    ;
    ; For systems with Synchronous Flash
    ;
    ;        ldr     r1,  =xlli_SXCNFG_value
    ;        str     r1,  [r4, #xlli_SXCNFG_offset]


    ; ***** STEP 3 *****
    ;

    ;
    ; ***** STEP 4 *****
    ;
    ; Appropriately configure, but don't enable, each SDRAM partition pair
    ;
    ldr     r1, =xlli_MDCNFG_value          ; Fetch platform value for MDCNFG

    bic     r1, r1,  #(xlli_MDCNFG_DE0 :OR: xlli_MDCNFG_DE1)   ; Disable all
    bic     r1, r1,  #(xlli_MDCNFG_DE2 :OR: xlli_MDCNFG_DE3)   ; SDRAM banks
    ;
    ;       Check for conditional def for 32 vs 16 bit bus width
    ;
    bic     r1, r1,  #xlli_MDCNFG_DWID0     ; Set banks 0/1 for 32 bit width
    bic     r1, r1,  #xlli_MDCNFG_DWID2     ; Set banks 2/3 for 32 bit width

    orr     r1, r1,  #xlli_BIT_11    ; This reserved bit should always be set
    orr     r1, r1,  #xlli_BIT_27    ; This reserved bit should always be set
    str     r1, [r4, #xlli_MDCNFG_offset]   ; Write w/o enabling SDRAM banks

    ;
    ; ***** STEP 5 *****  (Delay at least 200 uS)
    ;
    ldr     r2,  =xlli_OSTREGS_PHYSICAL_BASE ; Load OS timer base address
    ldr     r3,  [r2, #xlli_OSCR0_offset]    ; Fetch starting value of OSCR0
    add     r3,  r3,  #0x300                 ; Really 0x2E1 is about 200usec, so 0x300 should be plenty
xlli_5
    ldr     r1,  [r2, #xlli_OSCR0_offset]    ; Fetch current OSCR0 value
    cmp     r1,  r3                          ; Is the timer past the time out value?
    bmi     xlli_5                           ; No - Loop until it is
    ;
    ; ***** STEP 6 ***** (Make sure DCACHE is disabled)
    ;
    mrc     p15, 0, r2, c1, c0, 0           ; load r2 contents of register 1 in CP 15
    bic     r2,  r2,  #xlli_CONTROL_DCACHE  ; Disable D-Cache
    mcr     p15, 0, r2, c1, c0, 0           ; Write back to CP15
    ;
    ; ***** STEP 7 *****
    ;
    ;
    ; Access memory *not yet enabled* for CBR refresh cycles (8)
    ; - CBR is generated for all banks
    ;
    ldr     r1, =xlli_SDRAM_PHYSICAL_BASE
    str     r1, [r1]
    str     r1, [r1]
    str     r1, [r1]
    str     r1, [r1]
    str     r1, [r1]
    str     r1, [r1]
    str     r1, [r1]
    str     r1, [r1]

    str     r1, [r1]  ;  Fix for erratum #116. Makes up for ineffective 1st mem access.
                      ;  This is being left in for Bulverde for the moment
    ;
    ; ***** STEP 8 *****
    ;
    ;  Re-enable D-cache if desired (we don't)

    ;
    ; ***** STEP 9 *****
    ;
    ; Re-enable SDRAM partitions
    ;
    ldr     r2,  [r4, #xlli_MDCNFG_offset]   ; Fetch the current MDCNFG value
    bic     r2,  r2,  #xlli_MDCNFG_DE0       ; disable SDRAM bank 0
    bic     r2,  r2,  #xlli_MDCNFG_DE1       ; disable SDRAM bank 1
    orr     r2,  r2,  #xlli_MDCNFG_DE2       ; enable SDRAM bank 2
    bic     r2,  r2,  #xlli_MDCNFG_DE3       ; disable SDRAM bank 3
    str     r2,  [r4, #xlli_MDCNFG_offset]   ; Write back MDCNFG, enabling the SDRAM bank(s)
    ;
    ; ***** STEP 10 *****
    ;
    ; Write the MDMRS register to trigger an MRS command to all enabled banks of SDRAM.
    ;
    ;
    ldr     r1,  =xlli_MDMRS_value           ; Fetch platform MDMRS value
    str     r1,  [r4, #xlli_MDMRS_offset]    ; Write the MDMRS value back
    ;
    ; ***** STEP 11 *****
    ;
    ; In systems with SDRAM or Synchronous Flash, optionally enable auto-power-down by setting MDREFR:APD
    ;
    ldr     r3,  [r4, #xlli_MDREFR_offset]   ; Get MDREFR value
    orr     r3,  r3,  #xlli_MDREFR_APD       ; enable auto power down
    str     r3,  [r4, #xlli_MDREFR_offset]   ; Write value back

    mov     pc,  lr                         ; return to calling routine

        LTORG


;******************************************************************************
;
; FUNCTION: xlli_GPIO_init
; 
; Initialize GPIO subsystem
;
;******************************************************************************
    ALIGN
xlli_GPIO_init   

;       Get GPIO registers base address and configure all GPIO lines.
;
    ldr     r0,  =xlli_GPIOREGS_PHYSICAL_BASE   ; Load the GPIO register block base address

    ldr     r1,  =xlli_GPSR0_value              ; Get the pin set values for GPSR0
    str     r1,  [r0, #xlli_GPSR0_offset]       ; Write the R0 values

    ldr     r2,  =xlli_GPSR1_value              ; Get the pin set values for GPSR1
    str     r2,  [r0, #xlli_GPSR1_offset]       ; Write the R1 values

    ldr     r1,  =xlli_GPSR2_value              ; Get the pin set values for GPSR2
    str     r1,  [r0, #xlli_GPSR2_offset]       ; Write the R2 values

    ldr     r2,  =xlli_GPSR3_value              ; Get the pin set values for GPSR3
    str     r2,  [r0, #xlli_GPSR3_offset]       ; Write the R3 values

    ldr     r1,  =xlli_GPCR0_value              ; Get the pin clear values for GPCR0
    str     r1,  [r0, #xlli_GPCR0_offset]       ; Write the R0 values

    ldr     r2,  =xlli_GPCR1_value              ; Get the pin clear values for GPCR1
    str     r2,  [r0, #xlli_GPCR1_offset]       ; Write the R1 values

    ldr     r1,  =xlli_GPCR2_value              ; Get the pin clear values for GPCR2
    str     r1,  [r0, #xlli_GPCR2_offset]       ; Write the R2 values

    ldr     r2,  =xlli_GPCR3_value              ; Get the pin clear values for GPCR3
    str     r2,  [r0, #xlli_GPCR3_offset]       ; Write the R3 values

    ldr     r1,  =xlli_GPDR0_value              ; Get the pin direction values for GPDR0
    str     r1,  [r0, #xlli_GPDR0_offset]       ; Write the R0 values

    ldr     r2,  =xlli_GPDR1_value              ; Get the pin direction values for GPDR1
    str     r2,  [r0, #xlli_GPDR1_offset]       ; Write the R1 values

    ldr     r1,  =xlli_GPDR2_value              ; Get the pin direction values for GPDR2
    str     r1,  [r0, #xlli_GPDR2_offset]       ; Write the R2 values

    ldr     r2,  =xlli_GPDR3_value              ; Get the pin direction values for GPDR3
    str     r2,  [r0, #xlli_GPDR3_offset]       ; Write the R3 values

    ldr     r1,  =xlli_GAFR0_L_value            ; Get the pin alt function values for GAFR0_L
    str     r1,  [r0, #xlli_GAFR0_L_offset]     ; Write the R0_L values

    ldr     r2,  =xlli_GAFR0_U_value            ; Get the pin alt function values for GAFR0_U
    str     r2,  [r0, #xlli_GAFR0_U_offset]     ; Write the R0_U values

    ldr     r1,  =xlli_GAFR1_L_value            ; Get the pin alt function values for GAFR1_L
    str     r1,  [r0, #xlli_GAFR1_L_offset]     ; Write the R1_L values

    ldr     r2,  =xlli_GAFR1_U_value            ; Get the pin alt function values for GAFR1_U
    str     r2,  [r0, #xlli_GAFR1_U_offset]     ; Write the R1_U values

    ldr     r1,  =xlli_GAFR2_L_value            ; Get the pin alt function values for GAFR2_L
    str     r1,  [r0, #xlli_GAFR2_L_offset]     ; Write the R2_L values

    ldr     r2,  =xlli_GAFR2_U_value            ; Get the pin alt function values for GAFR2_U
    str     r2,  [r0, #xlli_GAFR2_U_offset]     ; Write the R2_U values

    ldr     r1,  =xlli_GAFR3_L_value            ; Get the pin alt function values for GAFR3_L
    str     r1,  [r0, #xlli_GAFR3_L_offset]     ; Write the R3_L values

    ldr     r2,  =xlli_GAFR3_U_value            ; Get the pin alt function values for GAFR3_U
    str     r2,  [r0, #xlli_GAFR3_U_offset]     ; Write the R3_U values

    ; The RDH and PH bits on Bulverde must be set to enable updated GPIO pins.
    ; These are sticky bits.
    ;
    ldr     r0, =xlli_PMRCREGS_PHYSICAL_BASE
    mov     r2, #(xlli_PSSR_PH | xlli_PSSR_RDH) ; Set the PH and RDH bits to enable all GPIOs
    str     r2, [r0, #xlli_PSSR_offset]         ; Enable all GPIO lines

    mov     r1, #0x600
xlli_g  subs    r1, r1, #1
    bne     xlli_g

    mov     pc, lr                              ; Return to calling program
    
    LTORG

        
    END