hwinit.s

Windows CE 6.0 BSP for VOIP sample phone. Intel PXA270 platform.

;
; Copyright (c) Microsoft Corporation.  All rights reserved.
;
;
; Use of this sample source code is subject to the terms of the Microsoft
; license agreement under which you licensed this sample source code. If
; you did not accept the terms of the license agreement, you are not
; authorized to use this sample source code. For the terms of the license,
; please see the license agreement between you and Microsoft or, if applicable,
; see the LICENSE.RTF on your install media or the root of your tools installation.
; THE SAMPLE SOURCE CODE IS PROVIDED "AS IS", WITH NO WARRANTIES OR INDEMNITIES.
;
;
;
; Copyright 2002-2003 Intel Corporation All Rights Reserved.
;**
;** Portions of the source code contained or described herein and all documents
;** related to such source code (Material) are owned by Intel Corporation
;** or its suppliers or licensors and is licensed by Microsoft Corporation for distribution.  
;** Title to the Material remains with Intel Corporation or its suppliers and licensors. 
;** Use of the Materials is subject to the terms of the Microsoft license agreement which accompanied the Materials.  
;** No other license under any patent, copyright, trade secret or other intellectual
;** property right is granted to or conferred upon you by disclosure or
;** delivery of the Materials, either expressly, by implication, inducement,
;** estoppel or otherwise 
;** Some portion of the Materials may be copyrighted by Microsoft Corporation.
;
;
;*********************************************************************************
;  FILENAME:    hwinit.s
;
;
;  PURPOSE:     Selected functions copied from xlli_lowlev_init.s to provide
;               low level init functions for bringing up a PXA27x platform
;
;  NOTES:       The functions in this source code are called via a branch
;               with link instruction. Unless otherwise specified, no system
;               stack is assumed and no registers are preserved.
;******************************************************************************


;******************************************************************************
; FUNCTION: FFUART_init
;
; Initialize FFUART (debug serial port for MDOCLDR)
;
;******************************************************************************
    ALIGN
FFUART_init

    ldr r1, =XLLP_FFUART_BASE_REG_PA

    ;1. Set FFUART Register
    ;

    ;Ensure that UART interrupts are turned off.
    mov r2, #0
    str r2, [r1, #xlli_uart_lcr_offset]         ; Clear DLAB
    str r2, [r1, #xlli_uart_ier_offset]         ; IER_DLH = 0x0
    
    ; Set the Baud Rate (Divisor low = DEBUG_BAUD_38400).
    ; The divisor latches are at offsets 0 and 1, which are 
    ; receive/transmit data and ier registers.
    mov r2, #0x80
    str r2, [r1, #xlli_uart_lcr_offset]         ; Access Divisor
    mov r2, #0x00000018                         ; DEBUG_BAUD_38400      
    str r2, [r1, #xlli_uart_thr_offset]         ; Low byte divisor  
    mov r2, #0x0
    str r2, [r1, #xlli_uart_ier_offset]         ; High byte divisor
    mov r2, #0x0
    str r2, [r1, #xlli_uart_lcr_offset]         ; Clear DLAB 

    ;Setting UART properties to 8N1 
    mov r2, #0x3                                ; 8 bits, 1 stop, no parity. Also LCR DLAB bit = 0.
    str r2, [r1, #xlli_uart_lcr_offset]         
    mov r2, #0x01                               ; Enable the FIFO
    str r2, [r1, #xlli_uart_fcr_offset]         
    mov r2, #0x07                               ; Clear Rx,Tx FIFOs
    str r2, [r1, #xlli_uart_fcr_offset]         

    ; Don't enable UART interrupts - we'll poll for the data.
    mov r2, #0
    str r2, [r1, #xlli_uart_ier_offset]        ; IER_DLH = 0x0

    ; Ensure loop-back test mode is off even though MCR reset value is 0x0. 
    mov r2, #0
    str r2, [r1, #xlli_uart_mcr_offset]        ; UART is in normal mode


    ; 2. Configure GPIO pins for FFUART 
    ;
    ; This is already done in GPIO_Init


    ; 3. turn on the FFUART clock
    ;
    ldr     r1, =xlli_CLKREGS_PHYSICAL_BASE
    ldr     r2, [r1, #xlli_CKEN_offset]
    orr     r2, r2, #XLLP_CKEN_FFUART
    str     r2, [r1, #xlli_CKEN_offset]

    ; 4. Enable the UART
    ldr r1, =XLLP_FFUART_BASE_REG_PA
    mov r2, #0x40
    str r2, [r1, #xlli_uart_ier_offset]    ; IER_DLH = 0x40

    mov  pc, lr          ; return to caller.


;******************************************************************************
;
; FUNCTION: WriteStringFFUART
;
; Writes to FFUART ASCII characters pointed to by r0. Stops when it
; encounters 00
;
; Input: r0 (pointer to the string)
; Destroys: r1, r2, r3, r4, lr
;
;******************************************************************************
    ALIGN
WriteStringFFUART
    
    mov r3, lr

    mov r4, r0          ;string pointer
    
writeStringFFUART_nextByte    
    ldrb r0, [r4]       ;load byte to r0
    cmp r0, #0          ;if 0 we are done
    beq writeStringFFUART_done
    bl WriteFFUART

    add r4, r4, #1
    b writeStringFFUART_nextByte
    
writeStringFFUART_done
    mov pc, r3

;******************************************************************************
;
; FUNCTION: WriteFFUART
;
; Writes to FFUART ASCII character in r0
; Input: r0
; Destroys: r1, r2, lr
;
;******************************************************************************
    ALIGN
WriteFFUART
    ldr r1, =XLLP_FFUART_BASE_REG_PA
spinFifoEmpty
    ;Spin if FIFO has more than half data
    ldr r2, [r1, #xlli_uart_lsr_offset]
    tst r2, #0x020
    ;if Z flag = 0 then loop
    beq spinFifoEmpty

    str r0, [r1, #xlli_uart_thr_offset]

    mov pc, lr          ;return to caller




;******************************************************************************
;
; FUNCTION: xlli_mem_init
; 
; Initialize Memory controller
; At the minimum:   set MSC0      (for MDOC on nCS0)
;                   set MDREFR    (refresh timings for SDRAM)
;                   set MDCNFG    (for SDRAM on nSDCS2)
;
; Notes: The sequence below is based on the recommended memory initializing steps
; detailed in the Bulverde EAS, Volume I (Section 13.17, page 13-72)
;
;******************************************************************************
    ALIGN
xlli_mem_init
        
    ;
    ;  STEP 0 - Delay 200 uS
    ;  *******************
    ;
    ldr     r2,  =xlli_OSTREGS_PHYSICAL_BASE ; Load OS timer base address
    ldr     r3,  [r2, #xlli_OSCR0_offset]    ; Fetch starting value of OSCR0
    add     r3,  r3,  #0x300                 ; Really 0x2E1 is about 200usec, so 0x300 should be plenty
xlli_3
    ldr     r1,  [r2, #xlli_OSCR0_offset]    ; Fetch current OSCR0 value
    cmp     r1,  r3                          ; Is the timer past the time out value?
    bmi     xlli_3                           ; No - Loop until it is
      

    ;
    ;  STEP 1 - 1st bullet: Write MSC0, MSC1 and MSC2 (the order is not important)
    ;  *******************
    ;
    ldr     r4,  =xlli_MEMORY_CONFIG_BASE   ; Get memory controller base address

    ; Set MSC0
    ; Nothing to set, use default values
    ; RBW0 should already be set to 1 by BOOT_SEL pin
    ;
    ; ldr     r1,  =0x7FF07FF8            ; Get MSC0 setting for Flash
    ; ldr     r1,  =xlli_MSC0_value            ; Get MSC0 setting for Flash
    ; str     r1,  [r4, #xlli_MSC0_offset]    ; Write the value out
    ; ldr     r1,  [r4, #xlli_MSC0_offset]    ; Read back to latch the data

    ldr     r2,  =xlli_MSC1_value           ; Get MSC1 setting
    str     r2,  [r4, #xlli_MSC1_offset]    ; Write the value out
    ldr     r2,  [r4, #xlli_MSC1_offset]    ; Read back to latch the data

    ldr     r1,  =xlli_MSC2_value           ; Get MSC2 setting
    str     r1,  [r4, #xlli_MSC2_offset]    ; Write the value out
    ldr     r1,  [r4, #xlli_MSC2_offset]    ; Read back to latch the data


    ;
    ;  STEP 1 - 2nd bullet: Write MECR, MCMEM0, MCMEM1, MCATT0, MCATT1, MCIO0, MCIO1 (order not important)
    ;  *******************
    ;
    ldr     r2,  =xlli_MECR_value           ; write MECR
    str     r2,  [r4, #xlli_MECR_offset]

    ldr     r1,  =xlli_MCMEM0_value         ; write MCMEM0
    str     r1,  [r4, #xlli_MCMEM0_offset]

    ldr     r2,  =xlli_MCMEM1_value         ; write MCMEM1
    str     r2,  [r4, #xlli_MCMEM1_offset]

    ldr     r1,  =xlli_MCATT0_value         ; write MCATT0
    str     r1,  [r4, #xlli_MCATT0_offset]

    ldr     r2,  =xlli_MCATT1_value         ; write MCATT1
    str     r2,  [r4, #xlli_MCATT1_offset]

    ldr     r1,  =xlli_MCIO0_value          ; write MCIO0
    str     r1,  [r4, #xlli_MCIO0_offset]