📄 startup.s
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;
; Copyright (c) Microsoft Corporation. All rights reserved.
;
;
; Use of this sample source code is subject to the terms of the Microsoft
; license agreement under which you licensed this sample source code. If
; you did not accept the terms of the license agreement, you are not
; authorized to use this sample source code. For the terms of the license,
; please see the license agreement between you and Microsoft or, if applicable,
; see the LICENSE.RTF on your install media or the root of your tools installation.
; THE SAMPLE SOURCE CODE IS PROVIDED "AS IS", WITH NO WARRANTIES OR INDEMNITIES.
;
INCLUDE kxarm.h
INCLUDE bulverde.inc
INCLUDE bulverde_macros.inc
INCLUDE xlli_bulverde_defs.inc
INCLUDE xlli_plato_defs.inc
INCLUDE plato.inc
INCLUDE image_cfg.inc
;---------------------------------------------------------
VERSION_MAJOR EQU "3"
VERSION_MINOR EQU "0"
XLLP_FFUART_BASE_REG_PA EQU (xlli_perif_base + xlli_ffuart_offset)
XLLP_CKEN_FFUART EQU xlli_BIT_6
;---------------------------------------------------------
TEXTAREA
; romimage needs pTOC. give it one.
pTOC DCD -1
EXPORT pTOC
;This marks the first instruction executed
STARTUPTEXT
LEAF_ENTRY StartUp
; Perform pre-initialization (enter supervisor mode, disable MMU and caches,
; and determine the reason for the reset).
; Put the CPU in Supervisor mode (SVC) and disable IRQ and FIQ interrupts.
;
ldr r0, =(Mode_SVC :OR: NoIntsMask)
msr cpsr_c, r0
; Disable the MMU, caches, and write-buffer and flush.
;
ldr r0, =0x2043 ; enable access to all coprocessors
mcr p15, 0, r0, c15, c1, 0 ;
CPWAIT r0 ;
ldr r0, =0x00000078 ; get a zero to turn things off (must write bits[6:3] as 1s)
mcr p15, 0, r0, c1, c0, 0 ; turn off MMU, I&D caches, and write buffer
CPWAIT r0 ;
mvn r0, #0 ; grant manager access to all domains
mcr p15, 0, r0, c3, c0, 0 ;
; Read the reset cause bits in RCSR.
;
ldr r0, =BULVERDE_BASE_REG_PA_PWR
ldr r10, [r0, #RCSR_OFFSET]
; Extract the reset cause bits.
;
mov r2, #RCSR_ALL ; Mask RCSR
and r10, r10, r2 ; r10 now holds the conditioned Reset Reason
; r10 now contains the contents of the power manager registers RCSR in the
; lower half and PSSR in the upper half. If we're in this routine because
; of a hardware/power-on reset, then we need to continue in this routine and
; initialize all hardware. Otherwise, we'll assume the hardware's already
; been initialized and we can skip.
;
; Bootstrap/Init the GPIO subsystem
; This is necessary because the SDRAM chip select is on a GPIO pin
; The startup code in the bootloader will re-initialize GPIO controller with
; the actual platform default values
;
bl xlli_GPIO_init
; Initialize the Bulverde memory controller.
;
bl xlli_mem_init
; If we're here because of a hardware reset then continue with hard reset
; startup and load the bootloader from flash into RAM
;
tst r10, #RCSR_HARD_RESET
bne Continue_HardReset_StartUp
; If we are here not because of a hardware reset (which means we could
; be resuming from a sleep), then jump to bootloader already in RAM, which
; will perform the sleep context restoration
;
b JumpToRamBootloader
Continue_HardReset_StartUp
; Init FFUART for serial debug output
;
bl FFUART_init
; Print MDOCLDR banner to serial port
;
adr r0, MDOCLDR_MESSAGE
bl WriteStringFFUART
; Load eboot from flash
; and jump to it.
;
b LoadEboot
MDOCLDR_MESSAGE DCB "\r\nMDOC LDR ", VERSION_MAJOR, ".", VERSION_MINOR, "\r\n", 0
;******************************************************************************
;
; FUNCTION: JumpToRamBootloader
;
; Jump to the RAM based bootloader that should already be loaded.
;
;******************************************************************************
ALIGN
JumpToRamBootloader
ldr pc, =EBOOT_RAM_ADDRESS
LTORG
INCLUDE hwinit.s
INCLUDE g3_startup.s
END
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