xllp_bcr.h

Windows CE 6.0 BSP for VOIP sample phone. Intel PXA270 platform.

#define XLLP_BCR_MISCWR2_MASK (~(XLLP_BCR_MISCWR2_RESERVED_BITS))


/* XLLP Miscellaneous Write Register 3 */

#define XLLP_BCR_MISCWR3_COMMS_SW_RESET (XLLP_BIT_0)
#define XLLP_BCR_MISCWR3_GPIO_RESET     (XLLP_BIT_1)
#define XLLP_BCR_MISCWR3_GPIO_RESET_EN  (XLLP_BIT_2)

#define XLLP_BCR_MISCWR3_RESERVED_BITS 0xFFFFFFF8u
#define XLLP_BCR_MISCWR3_MASK (~(XLLP_BCR_MISCWR3_RESERVED_BITS))


/* XLLP Miscellaneous Read Register 1 */

#define XLLP_BCR_MISCRR1_MMC_WP     (XLLP_BIT_0)
#define XLLP_BCR_MISCRR1_BTDCD      (XLLP_BIT_1)
#define XLLP_BCR_MISCRR1_BTRI       (XLLP_BIT_2)
#define XLLP_BCR_MISCRR1_BTDSR      (XLLP_BIT_3)
#define XLLP_BCR_MISCRR1_TS_BUSY    (XLLP_BIT_4)
#define XLLP_BCR_MISCRR1_USB_CBL    (XLLP_BIT_5)
#define XLLP_BCR_MISCRR1_nUSIM_CD   (XLLP_BIT_6)
#define XLLP_BCR_MISCRR1_nMMC_CD    (XLLP_BIT_7)
#define XLLP_BCR_MISCRR1_nMEMSTK_CD (XLLP_BIT_8)
#define XLLP_BCR_MISCRR1_nPENIRQ    (XLLP_BIT_9)
#define XLLP_BCR_MISCRR1_POLL_FLAG  (XLLP_BIT_10)

#define XLLP_BCR_MISCRR1_RESERVED_BITS 0xFFFFFC00u
#define XLLP_BCR_MISCRR1_MASK (~(XLLP_BCR_MISCRR1_RESERVED_BITS))

/* Platform Interrupt Mask/Enable Register 1 */

#define XLLP_BCR_INTMASK_ENABLE_R1_MMC          (XLLP_BIT_0)
#define XLLP_BCR_INTMASK_ENABLE_R1_USIM         (XLLP_BIT_1)
#define XLLP_BCR_INTMASK_ENABLE_R1_USBC         (XLLP_BIT_2)
#define XLLP_BCR_INTMASK_ENABLE_R1_ETHERNET     (XLLP_BIT_3)
#define XLLP_BCR_INTMASK_ENABLE_R1_AC97         (XLLP_BIT_4)
#define XLLP_BCR_INTMASK_ENABLE_R1_PENIRQ       (XLLP_BIT_5)
#define XLLP_BCR_INTMASK_ENABLE_R1_MSINS        (XLLP_BIT_6)
#define XLLP_BCR_INTMASK_ENABLE_R1_nEXBRD_INT   (XLLP_BIT_7)
#define XLLP_BCR_INTMASK_ENABLE_R1_S0_CD        (XLLP_BIT_9)
#define XLLP_BCR_INTMASK_ENABLE_R1_S0_STSCHG    (XLLP_BIT_10)
#define XLLP_BCR_INTMASK_ENABLE_R1_S0_IRQ       (XLLP_BIT_11)
#define XLLP_BCR_INTMASK_ENABLE_R1_S1_CD        (XLLP_BIT_13)
#define XLLP_BCR_INTMASK_ENABLE_R1_S1_STSCHG    (XLLP_BIT_14)
#define XLLP_BCR_INTMASK_ENABLE_R1_S1_IRQ       (XLLP_BIT_15)
#define XLLP_BCR_INTMASK_ENABLE_R1_PMC_IRQ      (XLLP_BIT_16)
#define XLLP_BCR_INTMASK_ENABLE_R1_BT_DTR_INT   (XLLP_BIT_17)
#define XLLP_BCR_INTMASK_ENABLE_R1_BT_RI_INT    (XLLP_BIT_18)
#define XLLP_BCR_INTMASK_ENABLE_R1_INT_Mx       (XLLP_BIT_19)

#define XLLP_BCR_INTMASK_ENABLE_R1_RESERVED_BITS 0xFFF01100u
#define XLLP_BCR_INTMASK_ENABLE_MASK (~(XLLP_BCR_INTMASK_ENABLE_R1_RESERVED_BITS))

/* Platform Interrupt Set/Clear Register 1 */

#define XLLP_BCR_INTSET_CLEAR_R1_MMC          (XLLP_BIT_0)
#define XLLP_BCR_INTSET_CLEAR_R1_USIM         (XLLP_BIT_1)
#define XLLP_BCR_INTSET_CLEAR_R1_USBC         (XLLP_BIT_2)
#define XLLP_BCR_INTSET_CLEAR_R1_ETHERNET     (XLLP_BIT_3)
#define XLLP_BCR_INTSET_CLEAR_R1_AC97         (XLLP_BIT_4)
#define XLLP_BCR_INTSET_CLEAR_R1_PENIRQ       (XLLP_BIT_5)
#define XLLP_BCR_INTSET_CLEAR_R1_MSINS        (XLLP_BIT_6)
#define XLLP_BCR_INTSET_CLEAR_R1_nEXBRD_INT   (XLLP_BIT_7)
#define XLLP_BCR_INTSET_CLEAR_R1_S0_CD        (XLLP_BIT_9)
#define XLLP_BCR_INTSET_CLEAR_R1_S0_STSCHG    (XLLP_BIT_10)
#define XLLP_BCR_INTSET_CLEAR_R1_S0_IRQ       (XLLP_BIT_11)
#define XLLP_BCR_INTSET_CLEAR_R1_S1_CD        (XLLP_BIT_13)
#define XLLP_BCR_INTSET_CLEAR_R1_S1_STSCHG    (XLLP_BIT_14)
#define XLLP_BCR_INTSET_CLEAR_R1_S1_IRQ       (XLLP_BIT_15)
#define XLLP_BCR_INTSET_CLEAR_R1_PMC_IRQ      (XLLP_BIT_16)
#define XLLP_BCR_INTSET_CLEAR_R1_BT_DTR_INT   (XLLP_BIT_17)
#define XLLP_BCR_INTSET_CLEAR_R1_BT_RI_INT    (XLLP_BIT_18)
#define XLLP_BCR_INTSET_CLEAR_R1_INT_Mx       (XLLP_BIT_19)

#define XLLP_BCR_INTSET_CLEAR_R1_RESERVED_BITS 0xFFF01100u
#define XLLP_BCR_INTSET_CLEAR_MASK (~(XLLP_BCR_INTSET_CLEAR_R1_RESERVED_BITS))

/* PCMCIA Socket0 Status/Control Register*/

#define XLLP_BCR_PCMCIA_SCR_S0_A0VPP        (XLLP_BIT_0)
#define XLLP_BCR_PCMCIA_SCR_S0_A1VPP        (XLLP_BIT_1)
#define XLLP_BCR_PCMCIA_SCR_S0_A0VCC        (XLLP_BIT_2)
#define XLLP_BCR_PCMCIA_SCR_S0_A1VCC        (XLLP_BIT_3)
#define XLLP_BCR_PCMCIA_SCR_S0_5V           (XLLP_BIT_0 | XLLP_BIT_1 | XLLP_BIT_2)
#define XLLP_BCR_PCMCIA_SCR_S0_3_3V         (XLLP_BIT_0 | XLLP_BIT_1 | XLLP_BIT_3)
#define XLLP_BCR_PCMCIA_SCR_S0_PWR          (XLLP_BIT_0 | XLLP_BIT_1 | XLLP_BIT_2 | XLLP_BIT_3)
#define XLLP_BCR_PCMCIA_SCR_S0_RESET        (XLLP_BIT_4)
#define XLLP_BCR_PCMCIA_SCR_S0_nCD          (XLLP_BIT_5)
#define XLLP_BCR_PCMCIA_SCR_S0_nVS1         (XLLP_BIT_6)
#define XLLP_BCR_PCMCIA_SCR_S0_nVS2         (XLLP_BIT_7)
#define XLLP_BCR_PCMCIA_SCR_S0_nVS          (XLLP_BIT_6 | XLLP_BIT_7)
#define XLLP_BCR_PCMCIA_SCR_S0_nSTSCHG_BVD1 (XLLP_BIT_8)
#define XLLP_BCR_PCMCIA_SCR_S0_nSPKR_BVD2   (XLLP_BIT_9)
#define XLLP_BCR_PCMCIA_SCR_S0_nIRQ         (XLLP_BIT_10)

#define XLLP_BCR_PCMCIA_SCR_S0_RESERVED_BITS    (0xF800u)
#define XLLP_BCR_PCMCIA_SCR_S0_MASK (~(XLLP_BCR_PCMCIA_SCR_S0_RESERVED_BITS))

/* PCMCIA Socket0 Status/Control Register*/

#define XLLP_BCR_PCMCIA_SCR_S1_A0VPP        (XLLP_BIT_0)
#define XLLP_BCR_PCMCIA_SCR_S1_A1VPP        (XLLP_BIT_1)
#define XLLP_BCR_PCMCIA_SCR_S1_A0VCC        (XLLP_BIT_2)
#define XLLP_BCR_PCMCIA_SCR_S1_A1VCC        (XLLP_BIT_3)
#define XLLP_BCR_PCMCIA_SCR_S1_5V           (XLLP_BIT_0 | XLLP_BIT_1 | XLLP_BIT_2)
#define XLLP_BCR_PCMCIA_SCR_S1_3_3V         (XLLP_BIT_0 | XLLP_BIT_1 | XLLP_BIT_3)
#define XLLP_BCR_PCMCIA_SCR_S1_PWR          (XLLP_BIT_0 | XLLP_BIT_1 | XLLP_BIT_2 | XLLP_BIT_3)
#define XLLP_BCR_PCMCIA_SCR_S1_RESET        (XLLP_BIT_4)
#define XLLP_BCR_PCMCIA_SCR_S1_nCD          (XLLP_BIT_5)
#define XLLP_BCR_PCMCIA_SCR_S1_nVS1         (XLLP_BIT_6)
#define XLLP_BCR_PCMCIA_SCR_S1_nVS2         (XLLP_BIT_7)
#define XLLP_BCR_PCMCIA_SCR_S1_nVS          (XLLP_BIT_6 | XLLP_BIT_7)
#define XLLP_BCR_PCMCIA_SCR_S1_nSTSCHG_BVD1 (XLLP_BIT_8)
#define XLLP_BCR_PCMCIA_SCR_S1_nSPKR_BVD2   (XLLP_BIT_9)
#define XLLP_BCR_PCMCIA_SCR_S1_nIRQ         (XLLP_BIT_10)

#define XLLP_BCR_PCMCIA_SCR_S1_RESERVED_BITS    (0xF800u)
#define XLLP_BCR_PCMCIA_SCR_S1_MASK (~(XLLP_BCR_PCMCIA_SCR_S1_RESERVED_BITS))

/* XLLP REVID (FPGA code revision ID) register */

#define XLLP_BCR_REVID_Z                (0x0Fu << 0)
#define XLLP_BCR_REVID_Y                (0x0Fu << 4)
#define XLLP_BCR_REVID_X                (0xFFu << 8)

#define XLLP_BCR_REVID_RESERVED_BITS    (0xFFFF0000u)
#define XLLP_BCR_REVID_MASK (~(XLLP_BCR_REVID_RESERVED_BITS))

/* XLLP Scratch (debug sleep storage) registers */

#define XLLP_BCR_SCRATCH_RESERVED_BITS  (0x00000000u)
#define XLLP_BCR_SCRATCH_MASK (~(XLLP_BCR_SCRATCH_RESERVED_BITS))

/*----------------------------------------------*/
/* XLLP SCR registers: not memory mapped        */

/* XLLP SCR  */

#define XLLP_BCR_SCR_DCID             (0x0Fu)
#define XLLP_BCR_SCR_DCREV            (XLLP_BIT_5 | XLLP_BIT_6 | XLLP_BIT_7)
#define XLLP_BCR_SCR_nBB_PRES         (XLLP_BIT_8)
#define XLLP_BCR_SCR_BBREV            (XLLP_BIT_9 | XLLP_BIT_10 | XLLP_BIT_11)
#define XLLP_BCR_SCR_nEXBID_PRES      (XLLP_BIT_12)
#define XLLP_BCR_SCR_EXBID            (XLLP_BIT_13 | XLLP_BIT_14)
#define XLLP_BCR_SCR_SWAP_FLASH       (XLLP_BIT_15)

#define XLLP_BCR_SCR_RESERVED_BITS    (0xFFFF0000u)
#define XLLP_BCR_SCR_MASK (~(XLLP_BCR_SCR_RESERVED_BITS))

/* XLLP SCR2  */

#define XLLP_BCR_SCR2_LCDID           (0x3Fu)
#define XLLP_BCR_SCR2_ORIENT          (XLLP_BIT_6)
#define XLLP_BCR_SCR2_AUDIOID         (XLLP_BIT_7 | XLLP_BIT_8 | XLLP_BIT_9)
#define XLLP_BCR_SCR2_nGFX_PRES       (XLLP_BIT_10)
#define XLLP_BCR_SCR2_nBB_PRES        (XLLP_BIT_11) // Questionable.  To be verified.

#define XLLP_BCR_SCR2_RESERVED_BITS    (0xFFFFFF00u)
#define XLLP_BCR_SCR2_MASK (~(XLLP_BCR2_SCR_RESERVED_BITS))


/* XLLP Board Control Register Primitive Functions */
/*
void XllpBcrWriteToHexLeds(P_XLLP_BCR_T,XLLP_UINT32_T);
void XllpBcrWriteDIGITxDPToHexLeds(P_XLLP_BCR_T,XLLP_UINT32_T);
void XllpBcrWriteDiscLeds(P_XLLP_BCR_T,XLLP_UINT32_T);
XLLP_UINT32_T XllpBcrReadRotSwt(P_XLLP_BCR);
XLLP_UINT32_T XllpBcrReadGpSwt(P_XLLP_BCR);
XLLP_UINT32_T XllpBcrReadMiscReadReg1(P_XLLP_BCR);
void XllpBcrModifyMiscWriteReg1(P_XLLP_BCR, XLLP_UINT32_T,XLLP_UINT32_T);
void XllpBcrModifyMiscWriteReg2(P_XLLP_BCR, XLLP_UINT32_T,XLLP_UINT32_T);
void XllpBcrPlatformInterruptMask_Enable(P_XLLP_BCR, XLLP_UINT32_T,XLLP_UINT32_T);
void XllpBcrPlatformInterruptSet_Clear(P_XLLP_BCR, XLLP_UINT32_T,XLLP_UINT32_T);
void XllpBcrWritePcmciaS0StatusControlReg(P_XLLP_BCR, XLLP_UINT32_T);
void XllpBcrWritePcmciaS1StatusControlReg(P_XLLP_BCR, XLLP_UINT32_T);
XLLP_UINT32_T XllpBcrReadPcmciaS0StatusControlReg(P_XLLP_BCR);
XLLP_UINT32_T XllpBcrReadPcmciaS1StatusControlReg(P_XLLP_BCR);
*/


#endif //__XLLP_BCR_H__